static int msenc_dma_wait_idle(struct platform_device *dev, u32 *timeout)
{
nvhost_dbg_fn("");
if (!*timeout)
*timeout = MSENC_IDLE_TIMEOUT_DEFAULT;
do {
u32 check = min_t(u32, MSENC_IDLE_CHECK_PERIOD, *timeout);
u32 dmatrfcmd = host1x_readl(dev, msenc_dmatrfcmd_r());
u32 idle_v = msenc_dmatrfcmd_idle_v(dmatrfcmd);
if (msenc_dmatrfcmd_idle_true_v() == idle_v) {
nvhost_dbg_fn("done");
return 0;
}
udelay(MSENC_IDLE_CHECK_PERIOD);
*timeout -= check;
} while (*timeout);
dev_err(&dev->dev, "dma idle timeout");
return -1;
}
int vi_disable_irq(struct vi *tegra_vi)
{
int val;
int err = 0;
err = nvhost_module_busy(tegra_vi->ndev);
if (err)
return err;
if (tegra_vi->ndev->id) {
/* Disable FIFO Overflow Interrupt */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_INTERRUPT_MASK_0,
0);
/* Reset status register */
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0);
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0,
val);
} else {
/* interrupts are associated only with master dev vi.0 */
disable_irq(tegra_vi->vi_irq);
/* Disable FIFO Overflow Interrupt */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_INTERRUPT_MASK_0,
0);
/* Reset status register */
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0);
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0,
val);
}
nvhost_module_idle(tegra_vi->ndev);
return 0;
}
static irqreturn_t vi_isr(int irq, void *dev_id)
{
struct vi *tegra_vi = (struct vi *)dev_id;
int val;
dev_dbg(&tegra_vi->ndev->dev, "%s: ++", __func__);
if (tegra_vi->ndev->id) {
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0);
/* changes required as per t124 register spec */
if (val & PPB_FIFO_OVRF)
atomic_inc(&(tegra_vi->vi_out.overflow));
/* Reset interrupt status register */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0,
val);
} else {
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0);
/* changes required as per t124 register spec */
if (val & PPA_FIFO_OVRF)
atomic_inc(&(tegra_vi->vi_out.overflow));
/* Reset interrupt status register */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0,
val);
}
schedule_work(&tegra_vi->stats_work);
return IRQ_HANDLED;
}
static int vic03_wait_mem_scrubbing(struct platform_device *dev)
{
int retries = VIC_IDLE_TIMEOUT_DEFAULT / VIC_IDLE_CHECK_PERIOD;
nvhost_dbg_fn("");
do {
u32 w = host1x_readl(dev, flcn_dmactl_r()) &
(flcn_dmactl_dmem_scrubbing_m() |
flcn_dmactl_imem_scrubbing_m());
if (!w) {
nvhost_dbg_fn("done");
return 0;
}
udelay(VIC_IDLE_CHECK_PERIOD);
} while (--retries || !tegra_platform_is_silicon());
nvhost_err(&dev->dev, "Falcon mem scrubbing timeout");
return -ETIMEDOUT;
}
static int msenc_wait_idle(struct platform_device *dev, u32 *timeout)
{
nvhost_dbg_fn("");
if (!*timeout)
*timeout = MSENC_IDLE_TIMEOUT_DEFAULT;
do {
u32 check = min_t(u32, MSENC_IDLE_CHECK_PERIOD, *timeout);
u32 w = host1x_readl(dev, msenc_idlestate_r());
if (!w) {
nvhost_dbg_fn("done");
return 0;
}
udelay(MSENC_IDLE_CHECK_PERIOD);
*timeout -= check;
} while (*timeout);
return -1;
}
/* note size here is a little over...*/
fw_name = kzalloc(32, GFP_KERNEL);
if (!fw_name)
return NULL;
decode_vic_ver(pdata->version, &maj, &min);
sprintf(fw_name, "vic%02d_ucode.bin", maj);
dev_info(&dev->dev, "fw name:%s\n", fw_name);
return fw_name;
}
#define VIC_IDLE_TIMEOUT_DEFAULT 10000 /* 10 milliseconds */
#define VIC_IDLE_CHECK_PERIOD 10 /* 10 usec */
static int vic03_flcn_wait_idle(struct platform_device *pdev,
u32 *timeout)
{
nvhost_dbg_fn("");
if (!*timeout)
*timeout = VIC_IDLE_TIMEOUT_DEFAULT;
do {
u32 check = min_t(u32, VIC_IDLE_CHECK_PERIOD, *timeout);
u32 w = host1x_readl(pdev, flcn_idlestate_r());
if (!w) {
nvhost_dbg_fn("done");
return 0;
}
udelay(VIC_IDLE_CHECK_PERIOD);
*timeout -= check;
} while (*timeout);
dev_err(&pdev->dev, "vic03 flcn idle timeout");
return -1;
}
static int vic03_flcn_dma_wait_idle(struct platform_device *pdev, u32 *timeout)
{
nvhost_dbg_fn("");
if (!*timeout)
*timeout = VIC_IDLE_TIMEOUT_DEFAULT;
do {
u32 check = min_t(u32, VIC_IDLE_CHECK_PERIOD, *timeout);
u32 dmatrfcmd = host1x_readl(pdev, flcn_dmatrfcmd_r());
u32 idle_v = flcn_dmatrfcmd_idle_v(dmatrfcmd);
if (flcn_dmatrfcmd_idle_true_v() == idle_v) {
nvhost_dbg_fn("done");
return 0;
}
udelay(VIC_IDLE_CHECK_PERIOD);
*timeout -= check;
} while (*timeout);
dev_err(&pdev->dev, "vic03 dma idle timeout");
return -1;
}
