void
com_gsc_attach(device_t parent, device_t self, void *aux)
{
struct com_gsc_softc *gsc = device_private(self);
struct com_softc *sc = &gsc->sc_com;
struct gsc_attach_args *ga = aux;
int pagezero_cookie;
bus_space_tag_t iot;
bus_space_handle_t ioh;
bus_addr_t iobase;
sc->sc_dev = self;
sc->sc_hwflags = 0;
sc->sc_swflags = 0;
iot = ga->ga_iot;
iobase = (bus_addr_t)ga->ga_hpa + COMGSC_OFFSET;
sc->sc_frequency = COMGSC_FREQUENCY;
/* Test if this is the console. Compare either HPA or device path. */
pagezero_cookie = hp700_pagezero_map();
if ((hppa_hpa_t)PAGE0->mem_cons.pz_hpa == ga->ga_hpa ) {
/*
* This port is the console. In this case we must call
* comcnattach() and later com_is_console() to initialize
* everything properly.
*/
if (comcnattach(iot, iobase, B9600,
sc->sc_frequency, COM_TYPE_NORMAL,
(TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) != 0) {
aprint_error(": can't comcnattach\n");
hp700_pagezero_unmap(pagezero_cookie);
return;
}
}
hp700_pagezero_unmap(pagezero_cookie);
/*
* Get the already initialized console ioh via com_is_console() if
* this is the console or map the I/O space if this isn't the console.
*/
if (!com_is_console(iot, iobase, &ioh) &&
bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh) != 0) {
aprint_error(": can't map I/O space\n");
return;
}
COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
com_attach_subr(sc);
gsc->sc_ih = hp700_intr_establish(sc->sc_dev, IPL_TTY,
comintr, sc, ga->ga_int_reg, ga->ga_irq);
}
/*
* Locate STI ROM.
* On some machines it may not be part of the HPA space.
*/
paddr_t
sti_sgc_getrom(struct confargs *ca)
{
paddr_t rom;
int pagezero_cookie;
rom = ca->ca_hpa;
if (ca->ca_type.iodc_sv_model != HPPA_FIO_GSGC) {
return rom;
}
switch (ca->ca_type.iodc_revision) {
case STI_GOPT1_REV:
case STI_GOPT2_REV:
case STI_GOPT3_REV:
case STI_GOPT4_REV:
case STI_GOPT5_REV:
case STI_GOPT6_REV:
case STI_GOPT7_REV:
/* these share the onboard's prom */
pagezero_cookie = hp700_pagezero_map();
rom = PAGE0->pd_resv2[1];
hp700_pagezero_unmap(pagezero_cookie);
break;
case STI_INEG_REV:
rom = STI_INEG_PROM;
break;
}
return rom;
}
void
hil_gsc_attach(device_t parent, device_t self, void *aux)
{
struct hil_gsc_softc *gsc = device_private(self);
struct hil_softc *sc = &gsc->sc_hs;
struct gsc_attach_args *ga = aux;
int pagezero_cookie;
sc->sc_dev = self;
sc->sc_bst = ga->ga_iot;
if (bus_space_map(ga->ga_iot, ga->ga_hpa,
HILMAPSIZE, 0, &sc->sc_bsh)) {
aprint_error(": couldn't map hil controller\n");
return;
}
pagezero_cookie = hp700_pagezero_map();
gsc->sc_hil_console = ga->ga_dp.dp_mod == PAGE0->mem_kbd.pz_dp.dp_mod &&
memcmp(ga->ga_dp.dp_bc, PAGE0->mem_kbd.pz_dp.dp_bc, 6) == 0;
hp700_pagezero_unmap(pagezero_cookie);
hil_attach(sc, &gsc->sc_hil_console);
gsc->sc_ih = hp700_intr_establish(IPL_TTY, hil_intr, sc,
ga->ga_ir, ga->ga_irq);
config_interrupts(self, hil_attach_deferred);
}
void
com_ssio_attach(device_t parent, device_t self, void *aux)
{
struct com_ssio_softc *sc_ssio = device_private(self);
struct com_softc *sc = &sc_ssio->sc_com;
struct ssio_attach_args *saa = aux;
int pagezero_cookie;
bus_addr_t iobase;
bus_space_handle_t ioh;
bus_space_tag_t iot;
sc->sc_dev = self;
iobase = saa->saa_iobase;
iot = saa->saa_iot;
if (bus_space_map(iot, iobase, COM_NPORTS,
0, &ioh)) {
aprint_error(": can't map I/O space\n");
return;
}
/* Test if this is the console. */
pagezero_cookie = hp700_pagezero_map();
if (PAGE0->mem_cons.pz_class == PCL_DUPLEX &&
PAGE0->mem_cons.pz_hpa == (struct iomod *)ioh) {
bus_space_unmap(iot, ioh, COM_NPORTS);
if (comcnattach(iot, iobase, B9600, COM_SSIO_FREQ,
COM_TYPE_NORMAL,
(TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) != 0) {
aprint_error(": can't comcnattach\n");
hp700_pagezero_unmap(pagezero_cookie);
return;
}
}
hp700_pagezero_unmap(pagezero_cookie);
sc->sc_frequency = COM_SSIO_FREQ;
COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
com_attach_subr(sc);
sc_ssio->sc_ih = ssio_intr_establish(IPL_TTY, saa->saa_irq,
comintr, sc, device_xname(self));
}
void
sti_sgc_attach(struct device *parent, struct device *self, void *aux)
{
struct sti_softc *sc = (void *)self;
struct confargs *ca = aux;
paddr_t rom;
u_int32_t romlen;
int rv;
int pagezero_cookie;
pagezero_cookie = hp700_pagezero_map();
sc->memt = sc->iot = ca->ca_iot;
sc->base = ca->ca_hpa;
/* we stashed rom addr/len into the last slot during probe */
rom = ca->ca_addrs[ca->ca_naddrs - 1].addr;
romlen = ca->ca_addrs[ca->ca_naddrs - 1].size;
if ((rv = bus_space_map(ca->ca_iot, rom, romlen, 0, &sc->romh))) {
if ((rom & HPPA_IOBEGIN) == HPPA_IOBEGIN)
sc->romh = rom;
else {
printf (": cannot map rom space (%d)\n", rv);
return;
}
}
#ifdef HP7300LC_CPU
/*
* PCXL2: enable accel I/O for this space, see PCX-L2 ERS "ACCEL_IO".
* "pcxl2_ers.{ps,pdf}", (section / chapter . rel. page / abs. page)
* 8.7.4 / 8-12 / 92, 11.3.14 / 11-14 / 122 and 14.8 / 14-5 / 203.
*/
if (strcmp(hppa_cpu_info->hppa_cpu_info_chip_type, "PCX-L2") == 0
&& ca->ca_hpa >= PCXL2_ACCEL_IO_START
&& ca->ca_hpa <= PCXL2_ACCEL_IO_END)
eaio_l2(PCXL2_ACCEL_IO_ADDR2MASK(ca->ca_hpa));
#endif /* HP7300LC_CPU */
sc->sc_devtype = bus_space_read_1(sc->iot, sc->romh, 3);
if (ca->ca_hpa == (hppa_hpa_t)PAGE0->mem_cons.pz_hpa)
sc->sc_flags |= STI_CONSOLE;
hp700_pagezero_unmap(pagezero_cookie);
sti_attach_common(sc);
}
void
memattach(struct device *parent, struct device *self, void *aux)
{
struct pdc_iodc_minit pdc_minit PDC_ALIGNMENT;
struct confargs *ca = aux;
struct mem_softc *sc = (struct mem_softc *)self;
int s, err, pagezero_cookie;
char bits[128];
printf (":");
pagezero_cookie = hp700_pagezero_map();
/* XXX check if we are dealing w/ Viper */
if (ca->ca_hpa == (hppa_hpa_t)VIPER_HPA) {
sc->sc_vp = (struct vi_trs *)
&((struct iomod *)ca->ca_hpa)->priv_trs;
/* XXX other values seem to blow it up */
if (sc->sc_vp->vi_status.hw_rev == 0) {
bitmask_snprintf(VI_CTRL, VIPER_BITS, bits,
sizeof(bits));
printf (" viper rev %x, ctrl %s",
sc->sc_vp->vi_status.hw_rev,
bits);
s = splhigh();
VI_CTRL |= VI_CTRL_ANYDEN;
((struct vi_ctrl *)&VI_CTRL)->core_den = 0;
((struct vi_ctrl *)&VI_CTRL)->sgc0_den = 0;
((struct vi_ctrl *)&VI_CTRL)->sgc1_den = 0;
((struct vi_ctrl *)&VI_CTRL)->core_prf = 1;
sc->sc_vp->vi_control = VI_CTRL;
splx(s);
#ifdef DEBUG
bitmask_snprintf(VI_CTRL, VIPER_BITS, bits,
sizeof(bits));
printf (" >> %s", bits);
#endif
} else
sc->sc_vp = NULL;
} else
sc->sc_vp = NULL;
if ((err = pdc_call((iodcio_t)pdc, 0, PDC_IODC, PDC_IODC_NINIT,
&pdc_minit, ca->ca_hpa, PAGE0->imm_spa_size)) < 0)
pdc_minit.max_spa = PAGE0->imm_max_mem;
hp700_pagezero_unmap(pagezero_cookie);
printf (" size %d", pdc_minit.max_spa / (1024*1024));
if (pdc_minit.max_spa % (1024*1024))
printf (".%d", pdc_minit.max_spa % (1024*1024));
printf ("MB");
/* L2 cache controller is a part of the memory controller on PCXL2 */
if (HPPA_PA_SPEC_MAJOR(hppa_cpu_info->hppa_cpu_info_pa_spec) == 1 &&
HPPA_PA_SPEC_MINOR(hppa_cpu_info->hppa_cpu_info_pa_spec) == 1 &&
HPPA_PA_SPEC_LETTER(hppa_cpu_info->hppa_cpu_info_pa_spec) == 'e') {
sc->sc_l2 = (struct l2_mioc *)ca->ca_hpa;
#ifdef DEBUG
bitmask_snprintf(sc->sc_l2->sltcv, SLTCV_BITS, bits,
sizeof(bits));
printf(", sltcv %s", bits);
#endif
/* sc->sc_l2->sltcv |= SLTCV_UP4COUT; */
if (sc->sc_l2->sltcv & SLTCV_ENABLE) {
uint32_t tagmask = sc->sc_l2->tagmask >> 20;
printf(", %dMB L2 cache", tagmask + 1);
}
