static inline void dpidle_pre_handler(void) { #ifndef CONFIG_MTK_FPGA #ifdef CONFIG_THERMAL //cancel thermal hrtimer for power saving tscpu_cancel_thermal_timer(); mtkts_bts_cancel_thermal_timer(); mtkts_btsmdpa_cancel_thermal_timer(); mtkts_pmic_cancel_thermal_timer(); mtkts_battery_cancel_thermal_timer(); mtkts_pa_cancel_thermal_timer(); mtkts_allts_cancel_thermal_timer(); mtkts_wmt_cancel_thermal_timer(); #endif #endif #if 0//FIXME: K2 early porting // disable gpu dvfs timer mtk_enable_gpu_dvfs_timer(false); // disable cpu dvfs timer hp_enable_timer(0); #endif }
static inline void dpidle_post_handler(void) { #if 0//FIXME: K2 early porting // disable cpu dvfs timer hp_enable_timer(1); // enable gpu dvfs timer mtk_enable_gpu_dvfs_timer(true); #endif #ifndef CONFIG_MTK_FPGA //restart thermal hrtimer for update temp info tscpu_start_thermal_timer(); #endif }
static inline void dpidle_pre_handler(void) { #ifndef CONFIG_MTK_FPGA //cancel thermal hrtimer for power saving tscpu_cancel_thermal_timer(); #endif #if 0//FIXME: K2 early porting // disable gpu dvfs timer mtk_enable_gpu_dvfs_timer(false); // disable cpu dvfs timer hp_enable_timer(0); #endif }
static inline void dpidle_post_handler(void) { #if 0 // disable cpu dvfs timer hp_enable_timer(1); // enable gpu dvfs timer mtk_enable_gpu_dvfs_timer(true); #endif #ifndef CONFIG_MTK_FPGA #ifdef CONFIG_THERMAL //restart thermal hrtimer for update temp info tscpu_start_thermal_timer(); mtkts_bts_start_thermal_timer(); mtkts_btsmdpa_start_thermal_timer(); mtkts_pmic_start_thermal_timer(); mtkts_battery_start_thermal_timer(); mtkts_pa_start_thermal_timer(); mtkts_allts_start_thermal_timer(); #endif #endif }