/* Check if a Write (data transfer from AP to CP) is * ongoing for a given HSI channel */ bool hsi_is_channel_busy(struct hsi_channel *ch) { struct hsi_port *p = ch->hsi_port; unsigned int port = p->port_number; unsigned int channel = ch->channel_number; unsigned int fifo; /* Data in FIFO is lost during the transition to RET or OFF modes */ fifo = hsi_fifo_get_id(p->hsi_controller, channel, port); if (hsi_get_rx_fifo_occupancy(p->hsi_controller, fifo) > 0) return true; if (ch->write_data.addr == NULL) return false; /* * Note: we do not check if there is a read pending, because incoming * data will trigger an interrupt (FIFO or DMA), and wake up the * platform, so no need to keep the clocks ON. */ return true; }
/** * hsi_ioctl - HSI I/O control * @dev - hsi device channel reference to apply the I/O control * (or port associated to it) * @command - HSI I/O control command * @arg - parameter associated to the control command. NULL, if no parameter. * * Return 0 on success, a negative value on failure. * */ int hsi_ioctl(struct hsi_device *dev, unsigned int command, void *arg) { struct hsi_channel *ch; struct hsi_dev *hsi_ctrl; struct hsi_port *pport; void __iomem *base; unsigned int port, channel; u32 acwake; int err = 0; int fifo = 0; u8 ret; struct hsi_platform_data *pdata; if (unlikely((!dev) || (!dev->ch) || (!dev->ch->hsi_port) || (!dev->ch->hsi_port->hsi_controller)) || (!(dev->ch->flags & HSI_CH_OPEN))) { pr_err(LOG_NAME "HSI IOCTL Invalid parameter\n"); return -EINVAL; } ch = dev->ch; pport = ch->hsi_port; hsi_ctrl = ch->hsi_port->hsi_controller; port = ch->hsi_port->port_number; channel = ch->channel_number; base = hsi_ctrl->base; dev_dbg(hsi_ctrl->dev, "IOCTL: ch %d, command %d\n", channel, command); spin_lock_bh(&hsi_ctrl->lock); hsi_clocks_enable_channel(hsi_ctrl->dev, channel, __func__); switch (command) { case HSI_IOCTL_ACWAKE_UP: /* Wake up request to Modem (typically OMAP initiated) */ /* Symetrical disable will be done in HSI_IOCTL_ACWAKE_DOWN */ if (ch->flags & HSI_CH_ACWAKE) { dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE UP\n"); err = -EPERM; goto out; } ch->flags |= HSI_CH_ACWAKE; pport->acwake_status |= BIT(channel); /* We only claim once the wake line per channel */ acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (!(acwake & HSI_WAKE(channel))) { hsi_outl(HSI_SET_WAKE(channel), base, HSI_SYS_SET_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_ACWAKE_DOWN: /* Low power request initiation (OMAP initiated, typically */ /* following inactivity timeout) */ /* ACPU HSI block shall still be capable of receiving */ if (!(ch->flags & HSI_CH_ACWAKE)) { dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE DOWN\n"); err = -EPERM; goto out; } acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (unlikely(pport->acwake_status != (acwake & HSI_WAKE_MASK))) { dev_warn(hsi_ctrl->dev, "ACWAKE shadow register mismatch" " acwake_status: 0x%x, HSI_SYS_WAKE_REG: 0x%x", pport->acwake_status, acwake); pport->acwake_status = acwake & HSI_WAKE_MASK; } /* SSI_TODO: add safety check for SSI also */ ch->flags &= ~HSI_CH_ACWAKE; pport->acwake_status &= ~BIT(channel); /* Release the wake line per channel */ if ((acwake & HSI_WAKE(channel))) { hsi_outl(HSI_CLEAR_WAKE(channel), base, HSI_SYS_CLEAR_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_SEND_BREAK: hsi_outl(1, base, HSI_HST_BREAK_REG(port)); /*HSI_TODO : need to deactivate clock after BREAK frames sent*/ /*Use interrupt ? (if TX BREAK INT exists)*/ break; case HSI_IOCTL_GET_ACWAKE: if (!arg) { err = -EINVAL; goto out; } *(u32 *)arg = hsi_inl(base, HSI_SYS_WAKE_REG(port)); break; case HSI_IOCTL_FLUSH_RX: ret = hsi_hsr_fifo_flush_channel(hsi_ctrl, port, channel); if (arg) *(size_t *)arg = ret; /* Ack the RX Int */ hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base, HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq, channel)); break; case HSI_IOCTL_FLUSH_TX: ret = hsi_hst_fifo_flush_channel(hsi_ctrl, port, channel); if (arg) *(size_t *)arg = ret; /* Ack the TX Int */ hsi_outl_and(~HSI_HST_DATAACCEPT(channel), base, HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq, channel)); break; case HSI_IOCTL_GET_CAWAKE: if (!arg) { err = -EINVAL; goto out; } err = hsi_get_cawake(dev->ch->hsi_port); if (err < 0) { err = -ENODEV; goto out; } *(u32 *)arg = err; break; case HSI_IOCTL_SET_RX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_GET_RX: if (!arg) { err = -EINVAL; goto out; } hsi_get_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_SET_TX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_GET_TX: if (!arg) { err = -EINVAL; goto out; } hsi_get_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_SW_RESET: dev_info(hsi_ctrl->dev, "SW Reset\n"); err = hsi_softreset(hsi_ctrl); /* Reset HSI config to default */ hsi_softreset_driver(hsi_ctrl); break; case HSI_IOCTL_GET_FIFO_OCCUPANCY: if (!arg) { err = -EINVAL; goto out; } fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO id found for " "channel %d.\n", channel); err = -EFAULT; goto out; } *(size_t *)arg = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo); break; case HSI_IOCTL_SET_WAKE_RX_3WIRES_MODE: dev_info(hsi_ctrl->dev, "Entering RX wakeup in 3 wires mode (no CAWAKE)\n"); pport->wake_rx_3_wires_mode = 1; /* HSI-C1BUG00085: ixxx: HSI wakeup issue in 3 wires mode * HSI will NOT generate the Swakeup for 2nd frame if it entered * IDLE after 1st received frame */ if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_ixxx_3WIRES_NO_SWAKEUP)) if (hsi_driver_device_is_hsi(to_platform_device (hsi_ctrl->dev))) hsi_set_pm_force_hsi_on(hsi_ctrl); /* When WAKE is not available, ACREADY must be set to 1 at * reset else remote will never have a chance to transmit. */ hsi_outl_or(HSI_SET_WAKE_3_WIRES | HSI_SET_WAKE_READY_LVL_1, base, HSI_SYS_SET_WAKE_REG(port)); hsi_driver_disable_interrupt(pport, HSI_CAWAKEDETECTED); break; case HSI_IOCTL_SET_WAKE_RX_4WIRES_MODE: dev_info(hsi_ctrl->dev, "Entering RX wakeup in 4 wires mode\n"); pport->wake_rx_3_wires_mode = 0; /* HSI-C1BUG00085: ixxx: HSI wakeup issue in 3 wires mode * HSI will NOT generate the Swakeup for 2nd frame if it entered * IDLE after 1st received frame */ if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_ixxx_3WIRES_NO_SWAKEUP)) if (hsi_driver_device_is_hsi(to_platform_device (hsi_ctrl->dev))) hsi_set_pm_default(hsi_ctrl); hsi_driver_enable_interrupt(pport, HSI_CAWAKEDETECTED); hsi_outl_and(HSI_SET_WAKE_3_WIRES_MASK, base, HSI_SYS_SET_WAKE_REG(port)); break; case HSI_IOCTL_SET_HI_SPEED: if (!arg) { err = -EINVAL; goto out; } hsi_ctrl->hsi_fclk_req = *(unsigned int *)arg ? HSI_FCLK_HI_SPEED : HSI_FCLK_LOW_SPEED; if (hsi_ctrl->hsi_fclk_req == hsi_ctrl->hsi_fclk_current) { dev_dbg(hsi_ctrl->dev, "HSI FClk already @%ldHz\n", hsi_ctrl->hsi_fclk_current); goto out; } if (hsi_is_controller_transfer_ongoing(hsi_ctrl)) { err = -EBUSY; goto out; } hsi_ctrl->clock_change_ongoing = true; spin_unlock_bh(&hsi_ctrl->lock); pdata = dev_get_platdata(hsi_ctrl->dev); /* Set the HSI FCLK to requested value. */ err = pdata->device_scale(hsi_ctrl->dev, hsi_ctrl->dev, hsi_ctrl->hsi_fclk_req); if (err < 0) { dev_err(hsi_ctrl->dev, "%s: Cannot set HSI FClk to" " %ldHz, err %d\n", __func__, hsi_ctrl->hsi_fclk_req, err); } else { dev_info(hsi_ctrl->dev, "HSI FClk changed from %ldHz to" " %ldHz\n", hsi_ctrl->hsi_fclk_current, hsi_ctrl->hsi_fclk_req); hsi_ctrl->hsi_fclk_current = hsi_ctrl->hsi_fclk_req; } spin_lock_bh(&hsi_ctrl->lock); hsi_ctrl->clock_change_ongoing = false; break; case HSI_IOCTL_GET_SPEED: if (!arg) { err = -EINVAL; goto out; } *(unsigned long *)arg = hsi_ctrl->hsi_fclk_current; break; default: err = -ENOIOCTLCMD; break; } out: /* All IOCTL end by disabling the clocks, except ACWAKE high. */ hsi_clocks_disable_channel(hsi_ctrl->dev, channel, __func__); spin_unlock_bh(&hsi_ctrl->lock); return err; }
/** * hsi_ioctl - HSI I/O control * @dev - hsi device channel reference to apply the I/O control * (or port associated to it) * @command - HSI I/O control command * @arg - parameter associated to the control command. NULL, if no parameter. * * Return 0 on success, a negative value on failure. * */ int hsi_ioctl(struct hsi_device *dev, unsigned int command, void *arg) { struct hsi_channel *ch; struct hsi_dev *hsi_ctrl; struct hsi_port *pport; void __iomem *base; unsigned int port, channel; u32 acwake; int err = 0; int fifo = 0; if (unlikely((!dev) || (!dev->ch) || (!dev->ch->hsi_port) || (!dev->ch->hsi_port->hsi_controller)) || (!(dev->ch->flags & HSI_CH_OPEN))) { pr_err(LOG_NAME "HSI IOCTL Invalid parameter\n"); return -EINVAL; } ch = dev->ch; pport = ch->hsi_port; hsi_ctrl = ch->hsi_port->hsi_controller; port = ch->hsi_port->port_number; channel = ch->channel_number; base = hsi_ctrl->base; dev_dbg(dev->device.parent, "IOCTL: ch %d, command %d\n", channel, command); spin_lock_bh(&hsi_ctrl->lock); hsi_clocks_enable_channel(dev->device.parent, channel, __func__); switch (command) { case HSI_IOCTL_ACWAKE_UP: if (ch->flags & HSI_CH_ACWAKE) { dev_dbg(dev->device.parent, "Duplicate ACWAKE UP\n"); err = -EPERM; goto out; } /* Wake up request to Modem (typically OMAP initiated) */ /* Symetrical disable will be done in HSI_IOCTL_ACWAKE_DOWN */ ch->flags |= HSI_CH_ACWAKE; pport->acwake_status |= BIT(channel); /* We only claim once the wake line per channel */ acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (!(acwake & HSI_WAKE(channel))) { hsi_outl(HSI_SET_WAKE(channel), base, HSI_SYS_SET_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_ACWAKE_DOWN: /* Low power request initiation (OMAP initiated, typically */ /* following inactivity timeout) */ /* ACPU HSI block shall still be capable of receiving */ if (!(ch->flags & HSI_CH_ACWAKE)) { dev_dbg(dev->device.parent, "Duplicate ACWAKE DOWN\n"); err = -EPERM; goto out; } acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (unlikely(pport->acwake_status != (acwake & HSI_WAKE_MASK))) { dev_warn(dev->device.parent, "ACWAKE shadow register mismatch" " acwake_status: 0x%x, HSI_SYS_WAKE_REG: 0x%x", pport->acwake_status, acwake); pport->acwake_status = acwake & HSI_WAKE_MASK; } /* SSI_TODO: add safety check for SSI also */ ch->flags &= ~HSI_CH_ACWAKE; pport->acwake_status &= ~BIT(channel); /* Release the wake line per channel */ if ((acwake & HSI_WAKE(channel))) { hsi_outl(HSI_CLEAR_WAKE(channel), base, HSI_SYS_CLEAR_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_SEND_BREAK: hsi_outl(1, base, HSI_HST_BREAK_REG(port)); /*HSI_TODO : need to deactivate clock after BREAK frames sent*/ /*Use interrupt ? (if TX BREAK INT exists)*/ break; case HSI_IOCTL_GET_ACWAKE: if (!arg) { err = -EINVAL; goto out; } *(u32 *)arg = hsi_inl(base, HSI_SYS_WAKE_REG(port)); break; case HSI_IOCTL_FLUSH_RX: hsi_outl(0, base, HSI_HSR_RXSTATE_REG(port)); break; case HSI_IOCTL_FLUSH_TX: hsi_outl(0, base, HSI_HST_TXSTATE_REG(port)); break; case HSI_IOCTL_GET_CAWAKE: if (!arg) { err = -EINVAL; goto out; } err = hsi_get_cawake(dev->ch->hsi_port); if (err < 0) { err = -ENODEV; goto out; } *(u32 *)arg = err; break; case HSI_IOCTL_SET_RX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_GET_RX: if (!arg) { err = -EINVAL; goto out; } hsi_get_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_SET_TX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_GET_TX: if (!arg) { err = -EINVAL; goto out; } hsi_get_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_SW_RESET: dev_info(dev->device.parent, "SW Reset\n"); err = hsi_softreset(hsi_ctrl); /* Reset HSI config to default */ hsi_softreset_driver(hsi_ctrl); break; case HSI_IOCTL_GET_FIFO_OCCUPANCY: if (!arg) { err = -EINVAL; goto out; } fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO id found for " "channel %d.\n", channel); err = -EFAULT; goto out; } *(size_t *)arg = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo); break; default: err = -ENOIOCTLCMD; break; } out: /* All IOCTL end by disabling the clocks, except ACWAKE high. */ hsi_clocks_disable_channel(dev->device.parent, channel, __func__); spin_unlock_bh(&hsi_ctrl->lock); return err; }
/* HSR_AVAILABLE interrupt processing */ static void hsi_do_channel_rx(struct hsi_channel *ch) { struct hsi_dev *hsi_ctrl = ch->hsi_port->hsi_controller; void __iomem *base = ch->hsi_port->hsi_controller->base; unsigned int n_ch; unsigned int n_p; unsigned int irq; long buff_offset; int rx_poll = 0; int data_read = 0; int fifo, fifo_words_avail; n_ch = ch->channel_number; n_p = ch->hsi_port->port_number; irq = ch->hsi_port->n_irq; dev_dbg(hsi_ctrl->dev, "Data Available interrupt for channel %d.\n", n_ch); /* Check if there is data in FIFO available for reading */ if (hsi_driver_device_is_hsi(to_platform_device(hsi_ctrl->dev))) { fifo = hsi_fifo_get_id(hsi_ctrl, n_ch, n_p); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO id found for " "channel %d.\n", n_ch); return; } fifo_words_avail = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo); if (!fifo_words_avail) { dev_dbg(hsi_ctrl->dev, "WARNING: RX FIFO %d empty before CPU copy\n", fifo); /* Do not disable interrupt becaue another interrupt */ /* can still come, this time with a real frame. */ return; } } /* Disable interrupts if not needed for polling */ if (!(ch->flags & HSI_CH_RX_POLL)) hsi_driver_disable_read_interrupt(ch); /* * Check race condition: RX transmission initiated but DMA transmission * already started - acknowledge then ignore interrupt occurence */ if (ch->read_data.lch != -1) { dev_warn(hsi_ctrl->dev, "Race condition between RX Int ch %d and DMA %0x\n", n_ch, ch->read_data.lch); goto done; } if (ch->flags & HSI_CH_RX_POLL) rx_poll = 1; if (ch->read_data.addr) { buff_offset = hsi_hsr_buffer_reg(hsi_ctrl, n_p, n_ch); if (buff_offset >= 0) { data_read = 1; *(ch->read_data.addr) = hsi_inl(base, buff_offset); } } hsi_reset_ch_read(ch); done: if (rx_poll) { spin_unlock(&hsi_ctrl->lock); hsi_port_event_handler(ch->hsi_port, HSI_EVENT_HSR_DATAAVAILABLE, (void *)n_ch); spin_lock(&hsi_ctrl->lock); } if (data_read) { spin_unlock(&hsi_ctrl->lock); dev_dbg(hsi_ctrl->dev, "Calling ch %d read callback.\n", n_ch); (*ch->read_done) (ch->dev, 1); spin_lock(&hsi_ctrl->lock); } }
static void do_hsi_gdd_lch(struct hsi_dev *hsi_ctrl, unsigned int gdd_lch) { void __iomem *base = hsi_ctrl->base; struct platform_device *pdev = to_platform_device(hsi_ctrl->dev); struct hsi_channel *ch; unsigned int port; unsigned int channel; unsigned int is_read_path; u32 gdd_csr; dma_addr_t dma_h; size_t size; int fifo, fifo_words_avail; if (hsi_get_info_from_gdd_lch(hsi_ctrl, gdd_lch, &port, &channel, &is_read_path) < 0) { dev_err(hsi_ctrl->dev, "Unable to match the DMA channel %d with" " an HSI channel\n", gdd_lch); return; } else { dev_dbg(hsi_ctrl->dev, "DMA event on gdd_lch=%d => port=%d, " "channel=%d, read=%d\n", gdd_lch, port, channel, is_read_path); } hsi_outl_and(~HSI_GDD_LCH(gdd_lch), base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); /* Warning : CSR register is cleared automaticaly by HW after SW read */ gdd_csr = hsi_inw(base, HSI_GDD_CSR_REG(gdd_lch)); if (!(gdd_csr & HSI_CSR_TOUT)) { if (is_read_path) { /* Read path */ dma_h = hsi_inl(base, HSI_GDD_CDSA_REG(gdd_lch)); size = hsi_inw(base, HSI_GDD_CEN_REG(gdd_lch)) * 4; dma_sync_single_for_cpu(hsi_ctrl->dev, dma_h, size, DMA_FROM_DEVICE); dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_FROM_DEVICE); ch = hsi_ctrl_get_ch(hsi_ctrl, port, channel); hsi_reset_ch_read(ch); dev_dbg(hsi_ctrl->dev, "Calling ch %d read callback " "(size %d).\n", channel, size/4); spin_unlock(&hsi_ctrl->lock); ch->read_done(ch->dev, size / 4); spin_lock(&hsi_ctrl->lock); /* Check if FIFO is correctly emptied */ if (hsi_driver_device_is_hsi(pdev)) { fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO " "id found for channel %d.\n", channel); return; } fifo_words_avail = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo); if (fifo_words_avail) dev_dbg(hsi_ctrl->dev, "FIFO %d not empty " "after DMA copy, remaining " "%d/%d frames\n", fifo, fifo_words_avail, HSI_HSR_FIFO_SIZE); } /* Re-enable interrupts for polling if needed */ if (ch->flags & HSI_CH_RX_POLL) hsi_driver_enable_read_interrupt(ch, NULL); } else { /* Write path */ dma_h = hsi_inl(base, HSI_GDD_CSSA_REG(gdd_lch)); size = hsi_inw(base, HSI_GDD_CEN_REG(gdd_lch)) * 4; dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_TO_DEVICE); ch = hsi_ctrl_get_ch(hsi_ctrl, port, channel); hsi_reset_ch_write(ch); dev_dbg(hsi_ctrl->dev, "Calling ch %d write callback " "(size %d).\n", channel, size/4); spin_unlock(&hsi_ctrl->lock); ch->write_done(ch->dev, size / 4); spin_lock(&hsi_ctrl->lock); } } else { dev_err(hsi_ctrl->dev, "Time-out overflow Error on GDD transfer" " on gdd channel %d\n", gdd_lch); spin_unlock(&hsi_ctrl->lock); /* TODO : need to perform a DMA soft reset */ hsi_port_event_handler(&hsi_ctrl->hsi_port[port - 1], HSI_EVENT_ERROR, NULL); spin_lock(&hsi_ctrl->lock); } }
/** * hsi_driver_read_dma - Program GDD [DMA] to write data to memory from * the hsi channel buffer. * @hsi_channel - pointer to the hsi_channel to read data from. * @data - 32-bit word pointer where to store the incoming data. * @size - Number of 32bit words to be transfered to the buffer. * * hsi_controller lock must be held before calling this function. * * Return 0 on success and < 0 on error. */ int hsi_driver_read_dma(struct hsi_channel *hsi_channel, u32 * data, unsigned int count) { struct hsi_dev *hsi_ctrl = hsi_channel->hsi_port->hsi_controller; void __iomem *base = hsi_ctrl->base; unsigned int port = hsi_channel->hsi_port->port_number; unsigned int channel = hsi_channel->channel_number; unsigned int sync; int lch; dma_addr_t src_addr; dma_addr_t dest_addr; u16 tmp; int fifo; lch = hsi_get_free_lch(hsi_ctrl); if (lch < 0) { dev_err(hsi_ctrl->dev, "No free DMA channels.\n"); return -EBUSY; /* No free GDD logical channels. */ } else { dev_dbg(hsi_ctrl->dev, "Allocated DMA channel %d for read on" " HSI channel %d.\n", lch, hsi_channel->channel_number); } /* When DMA is used for Rx, disable the Rx Interrupt. * (else DATAAVAILLABLE event would get triggered on first * received data word) * (Rx interrupt might be active for polling feature) */ hsi_driver_disable_read_interrupt(hsi_channel); /* * NOTE: Gettting a free gdd logical channel and * reserve it must be done atomicaly. */ hsi_channel->read_data.lch = lch; /* Sync is required for SSI but not for HSI */ sync = hsi_sync_table[HSI_SYNC_READ][port - 1][channel]; dest_addr = dma_map_single(hsi_ctrl->dev, data, count * 4, DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(hsi_ctrl->dev, dest_addr))) { dev_err(hsi_ctrl->dev, "Failed to create DMA read mapping.\n"); return -ENOMEM; } tmp = HSI_DST_BURST_4x32_BIT | HSI_DST_MEMORY_PORT | HSI_SRC_BURST_4x32_BIT | HSI_SRC_PERIPHERAL_PORT | HSI_DATA_TYPE_S32; hsi_outw(tmp, base, HSI_GDD_CSDP_REG(lch)); tmp = HSI_DST_AMODE_POSTINC | HSI_SRC_AMODE_CONST | sync; hsi_outw(tmp, base, HSI_GDD_CCR_REG(lch)); hsi_outw((HSI_BLOCK_IE | HSI_TOUT_IE), base, HSI_GDD_CCIR_REG(lch)); if (hsi_driver_device_is_hsi(to_platform_device(hsi_ctrl->dev))) { fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO id for DMA " "transfer from FIFO.\n"); return -EFAULT; } /* HSI CSSA register takes a FIFO ID when copying from FIFO */ hsi_outl(fifo, base, HSI_GDD_CSSA_REG(lch)); } else{ src_addr = hsi_ctrl->phy_base + HSI_HSR_BUFFER_CH_REG(port, channel); /* SSI CSSA register always takes a 32-bit address */ hsi_outl(src_addr, base, HSI_GDD_CSSA_REG(lch)); } /* HSI CDSA register takes a 32-bit address when copying to memory */ /* SSI CDSA register always takes a 32-bit address */ hsi_outl(dest_addr, base, HSI_GDD_CDSA_REG(lch)); hsi_outw(count, base, HSI_GDD_CEN_REG(lch)); /* TODO : Need to clean interrupt status here to avoid spurious int */ hsi_outl_or(HSI_GDD_LCH(lch), base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); hsi_outw_or(HSI_CCR_ENABLE, base, HSI_GDD_CCR_REG(lch)); return 0; }
/** * hsi_driver_write_dma - Program GDD [DMA] to write data from memory to * the hsi channel buffer. * @hsi_channel - pointer to the hsi_channel to write data to. * @data - 32-bit word pointer to the data. * @size - Number of 32bit words to be transfered. * * hsi_controller lock must be held before calling this function. * * Return 0 on success and < 0 on error. */ int hsi_driver_write_dma(struct hsi_channel *hsi_channel, u32 * data, unsigned int size) { struct hsi_dev *hsi_ctrl = hsi_channel->hsi_port->hsi_controller; void __iomem *base = hsi_ctrl->base; unsigned int port = hsi_channel->hsi_port->port_number; unsigned int channel = hsi_channel->channel_number; unsigned int sync; int lch; dma_addr_t src_addr; dma_addr_t dest_addr; u16 tmp; int fifo; if ((size < 1) || (data == NULL)) return -EINVAL; lch = hsi_get_free_lch(hsi_ctrl); if (lch < 0) { dev_err(hsi_ctrl->dev, "No free DMA channels.\n"); return -EBUSY; /* No free GDD logical channels. */ } else { dev_dbg(hsi_ctrl->dev, "Allocated DMA channel %d for write on" " HSI channel %d.\n", lch, hsi_channel->channel_number); } /* NOTE: Getting a free gdd logical channel and * reserve it must be done atomicaly. */ hsi_channel->write_data.lch = lch; /* Sync is required for SSI but not for HSI */ sync = hsi_sync_table[HSI_SYNC_WRITE][port - 1][channel]; src_addr = dma_map_single(hsi_ctrl->dev, data, size * 4, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(hsi_ctrl->dev, src_addr))) { dev_err(hsi_ctrl->dev, "Failed to create DMA write mapping.\n"); return -ENOMEM; } tmp = HSI_SRC_BURST_4x32_BIT| HSI_SRC_MEMORY_PORT | HSI_DST_BURST_4x32_BIT | HSI_DST_PERIPHERAL_PORT | HSI_DATA_TYPE_S32; hsi_outw(tmp, base, HSI_GDD_CSDP_REG(lch)); tmp = HSI_SRC_AMODE_POSTINC | HSI_DST_AMODE_CONST | sync; hsi_outw(tmp, base, HSI_GDD_CCR_REG(lch)); hsi_outw((HSI_BLOCK_IE | HSI_TOUT_IE), base, HSI_GDD_CCIR_REG(lch)); if (hsi_driver_device_is_hsi(to_platform_device(hsi_ctrl->dev))) { fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO id for DMA " "transfer to FIFO.\n"); return -EFAULT; } /* HSI CDSA register takes a FIFO ID when copying to FIFO */ hsi_outl(fifo, base, HSI_GDD_CDSA_REG(lch)); } else { dest_addr = hsi_ctrl->phy_base + HSI_HST_BUFFER_CH_REG(port, channel); /* SSI CDSA register always takes a 32-bit address */ hsi_outl(dest_addr, base, HSI_GDD_CDSA_REG(lch)); } /* HSI CSSA register takes a 32-bit address when copying from memory */ /* SSI CSSA register always takes a 32-bit address */ hsi_outl(src_addr, base, HSI_GDD_CSSA_REG(lch)); hsi_outw(size, base, HSI_GDD_CEN_REG(lch)); /* TODO : Need to clean interrupt status here to avoid spurious int */ hsi_outl_or(HSI_GDD_LCH(lch), base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); hsi_outw_or(HSI_CCR_ENABLE, base, HSI_GDD_CCR_REG(lch)); return 0; }