static sw_error_t _horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) { sw_error_t rv; a_uint32_t reg, field; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, (a_uint8_t *) (®), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); field = reg & (0x1 << port_id); if (field) { *enable = A_FALSE; } else { *enable = A_TRUE; } return SW_OK; }
static sw_error_t _horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, fal_fwd_cmd_t cmd) { sw_error_t rv; a_uint32_t data; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (FAL_MAC_FRWRD == cmd) { SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data); } else if (FAL_MAC_DROP == cmd) { SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data); } else if (FAL_MAC_RDT_TO_CPU == cmd) { SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data); } else { return SW_NOT_SUPPORTED; } HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), sizeof (a_uint32_t)); return rv; }
static sw_error_t _horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) { sw_error_t rv; a_uint32_t data; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, (a_uint8_t *) (&data), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (A_TRUE == enable) { data &= (~((a_uint32_t)0x1 << port_id)); } else if (A_FALSE == enable) { data |= (0x1 << port_id); } else { return SW_BAD_PARAM; } HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, (a_uint8_t *) (&data), sizeof (a_uint32_t)); return rv; }
static sw_error_t _horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, fal_fwd_cmd_t * action) { sw_error_t rv; a_uint32_t data; a_uint32_t port_lock_en, port_drop_en; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data); SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data); if (1 == port_lock_en) { if (1 == port_drop_en) { *action = FAL_MAC_DROP; } else { *action = FAL_MAC_RDT_TO_CPU; } } else { *action = FAL_MAC_FRWRD; } return SW_OK; }
static sw_error_t _horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_speed_t speed) { sw_error_t rv; a_uint32_t phy_id = 0; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); if (FAL_SPEED_100 < speed) { return SW_BAD_PARAM; } rv = f2_phy_set_speed(dev_id, phy_id, speed); return rv; }
static sw_error_t _athena_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) { sw_error_t rv; a_uint32_t reg = 0; HSL_DEV_ID_CHECK(dev_id); if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg); HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (FAL_FDB_DEL_STATIC & flag) { rv = athena_fdb_commit(dev_id, ARL_FLUSH_PORT_UNICAST); } else { return SW_NOT_SUPPORTED; } return rv; }
static sw_error_t _garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } if (A_TRUE == enable) { val = 1; } else if (A_FALSE == enable) { val = 0; } else { return SW_BAD_PARAM; } HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); return rv; }
static sw_error_t _horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) { sw_error_t rv; a_uint32_t force, reg; if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); if (0 == force) { *enable = A_TRUE; } else { *enable = A_FALSE; } return SW_OK; }
static sw_error_t _shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (val) { *enable = A_TRUE; } else { *enable = A_FALSE; } return SW_OK; }
static sw_error_t _horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * autoadv) { sw_error_t rv; a_uint32_t phy_id; hsl_phy_ops_t *phy_drv; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); if (NULL == phy_drv->phy_autoneg_adv_get) return SW_NOT_SUPPORTED; rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); *autoadv = 0; rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv); SW_RTN_ON_ERROR(rv); return SW_OK; }
static sw_error_t _garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, fal_pt_1qmode_t * pport_1qmode) { sw_error_t rv; a_uint32_t regval = 0; fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, FAL_1Q_CHECK, FAL_1Q_SECURE }; HSL_DEV_ID_CHECK(dev_id); if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } SW_RTN_ON_NULL(pport_1qmode); HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, (a_uint8_t *) (®val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); *pport_1qmode = retval[regval & 0x3]; return SW_OK; }
static sw_error_t _garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, fal_pt_1q_egmode_t port_egvlanmode) { sw_error_t rv; a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3 }; HSL_DEV_ID_CHECK(dev_id); if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } if (FAL_EG_MODE_BUTT <= port_egvlanmode) { return SW_BAD_PARAM; } if (FAL_EG_HYBRID == port_egvlanmode) { return SW_NOT_SUPPORTED; } HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, (a_uint8_t *) (®val[port_egvlanmode]), sizeof (a_uint32_t)); return rv; }
static sw_error_t _horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (1 == val) { *enable = A_TRUE; } else { *enable = A_FALSE; } return rv; }
static sw_error_t _garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); if (val) { *enable = A_TRUE; } else { *enable = A_FALSE; } return SW_OK; }
static sw_error_t _garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, fal_pt_1qmode_t port_1qmode) { sw_error_t rv; a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; HSL_DEV_ID_CHECK(dev_id); if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } if (FAL_1Q_MODE_BUTT <= port_1qmode) { return SW_BAD_PARAM; } HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, (a_uint8_t *) (®val[port_1qmode]), sizeof (a_uint32_t)); return rv; }
static sw_error_t _garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } if ((0 == vid) || (vid > MAX_VLAN_ID)) { return SW_BAD_PARAM; } val = vid; HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, PORT_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); return rv; }
static sw_error_t _garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t mem_port_map) { sw_error_t rv; HSL_DEV_ID_CHECK(dev_id); if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), sizeof (a_uint32_t)); return rv; }
static sw_error_t _garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, fal_pt_1q_egmode_t * pport_egvlanmode) { sw_error_t rv; a_uint32_t regval = 0; fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, FAL_EG_TAGGED }; HSL_DEV_ID_CHECK(dev_id); if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } SW_RTN_ON_NULL(pport_egvlanmode); HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, (a_uint8_t *) (®val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); *pport_egvlanmode = retval[regval & 0x3]; return SW_OK; }
static sw_error_t _horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } if (A_TRUE == enable) { val = 1; } else if (A_FALSE == enable) { val = 0; } else { return SW_BAD_PARAM; } HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); return rv; }
static sw_error_t _horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_speed_t speed) { sw_error_t rv; a_uint32_t phy_id = 0; hsl_phy_ops_t *phy_drv; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); if (NULL == phy_drv->phy_speed_set) return SW_NOT_SUPPORTED; rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); if (FAL_SPEED_100 < speed) { return SW_BAD_PARAM; } rv = phy_drv->phy_speed_set(dev_id, phy_id, speed); return rv; }
static sw_error_t _athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_duplex_t duplex) { sw_error_t rv; a_uint32_t phy_id = 0; a_uint32_t reg_save = 0; a_uint32_t reg_val = 0; hsl_phy_ops_t *phy_drv; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); if (NULL == phy_drv->phy_duplex_set) return SW_NOT_SUPPORTED; if (FAL_DUPLEX_BUTT <= duplex) { return SW_BAD_PARAM; } rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); //save reg value HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®_val), sizeof (a_uint32_t)); reg_save = reg_val; SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); //set mac be config by sw and turn off RX TX MAC_EN HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®_val), sizeof (a_uint32_t)); rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex); //retore reg value HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®_save), sizeof (a_uint32_t)); return rv; }
static sw_error_t _isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (port_id != MIRROR_ANALYZER_NONE) { if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } } val = port_id; HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM, (a_uint8_t *) (&val), sizeof (a_uint32_t)); return rv; }
static sw_error_t _isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, fal_port_t port_id, fal_stp_state_t * state) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (FAL_SINGLE_STP_ID != st_id) { return SW_BAD_PARAM; } if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); switch (val) { case ISIS_STP_BLOCKING: *state = FAL_STP_BLOKING; break; case ISIS_STP_LISTENING: *state = FAL_STP_LISTENING; break; case ISIS_STP_LEARNING: *state = FAL_STP_LEARNING; break; case ISIS_STP_FARWARDING: *state = FAL_STP_FARWARDING; break; case ISIS_PORT_DISABLED: *state = FAL_STP_DISABLED; break; default: return SW_FAIL; } return SW_OK; }
static sw_error_t _athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) { sw_error_t rv; a_uint32_t phy_id; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); rv = f2_phy_restart_autoneg(dev_id, phy_id); return rv; }
static sw_error_t _horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) { sw_error_t rv; a_uint32_t val, force, reg; if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } if (A_TRUE == enable) { val = 1; } else if (A_FALSE == enable) { val = 0; } else { return SW_BAD_PARAM; } HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); if (force) { /* flow control isn't in force mode so can't set */ return SW_DISABLE; } SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®), sizeof (a_uint32_t)); return rv; }
static sw_error_t _athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) { sw_error_t rv; a_uint32_t phy_id = 0; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); rv = f2_phy_get_hibernate(dev_id, phy_id, enable); return rv; }
static sw_error_t _garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, PORT_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); *vid = val & 0xfff; return rv; }
static sw_error_t _horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_duplex_t * pduplex) { sw_error_t rv; a_uint32_t phy_id; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); rv = f2_phy_get_duplex(dev_id, phy_id, pduplex); return rv; }
static sw_error_t _horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, fal_port_t port_id, fal_stp_state_t state) { sw_error_t rv; a_uint32_t val; HSL_DEV_ID_CHECK(dev_id); if (FAL_SINGLE_STP_ID != st_id) { return SW_BAD_PARAM; } if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) { return SW_BAD_PARAM; } switch (state) { case FAL_STP_BLOKING: val = HORUS_STP_BLOCKING; break; case FAL_STP_LISTENING: val = HORUS_STP_LISTENING; break; case FAL_STP_LEARNING: val = HORUS_STP_LEARNING; break; case FAL_STP_FARWARDING: val = HORUS_STP_FARWARDING; break; case FAL_STP_DISABLED: val = HORUS_PORT_DISABLED; break; default: return SW_BAD_PARAM; } HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); return rv; }
static sw_error_t _horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) { sw_error_t rv; a_uint32_t force, reg; if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { return SW_BAD_PARAM; } HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); if (force != (a_uint32_t) enable) { return SW_OK; } if (A_TRUE == enable) { SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg); } else if (A_FALSE == enable) { SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg); } else { return SW_BAD_PARAM; } SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg); HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, (a_uint8_t *) (®), sizeof (a_uint32_t)); return rv; }