unsigned long
rtc_time_s3c2410(unsigned base)
{
struct tm tm;
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "s3c2410", 0);
hwi_add_location(base, S3C2410_RTC_SIZE, 0, hwi_find_as(base, 1));
// get the current time from the RTC, and convert it to seconds since epoch
chip_access(base, 0, 0, S3C2410_RTC_SIZE);
// enable RTC
chip_write8(S3C2410_RTCCON, chip_read8(S3C2410_RTCCON) | 1);
// convert BCD to binary
tm.tm_sec = bcd2bin(chip_read8(S3C2410_BCDSEC) & 0xff); // seconds
tm.tm_min = bcd2bin(chip_read8(S3C2410_BCDMIN) & 0xff); // minutes
tm.tm_hour = bcd2bin(chip_read8(S3C2410_BCDHOUR) & 0xff); // hours
tm.tm_mday = bcd2bin(chip_read8(S3C2410_BCDDAY) & 0xff); // day
tm.tm_mon = bcd2bin(chip_read8(S3C2410_BCDMON) & 0xff) -1; // month
tm.tm_year = (bcd2bin(chip_read8(S3C2410_BCDYEAR) & 0xff))+100; // year
chip_done();
return(calc_time_t(&tm));
}
unsigned long
rtc_time_none() {
//Tell Neutrino we don't have any RTC hardware on this board
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "NONE", 0);
return 0;
}
unsigned long
rtc_time_omap(unsigned base)
{
struct tm tm;
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "omap", 0);
hwi_add_location(base, OMAP_RTC_SIZE, 0, hwi_find_as(base, 1));
// get the current time from the RTC, and convert it to seconds since epoch
chip_access(base, 0, 0, OMAP_RTC_SIZE);
// start the RTC, if it's not already running
chip_write32(OMAP_RTC_CTRL, 0x01);
// convert BCD to binary
tm.tm_sec = bcd2bin(chip_read32(OMAP_RTC_SECONDS) & 0xff); // seconds
tm.tm_min = bcd2bin(chip_read32(OMAP_RTC_MINUTES) & 0xff); // minutes
tm.tm_hour = bcd2bin(chip_read32(OMAP_RTC_HOURS) & 0xff); // hours
tm.tm_mday = bcd2bin(chip_read32(OMAP_RTC_DAYS) & 0xff); // day
tm.tm_mon = bcd2bin(chip_read32(OMAP_RTC_MONTHS) & 0xff); // month
tm.tm_year = (bcd2bin(chip_read32(OMAP_RTC_YEARS) & 0xff))+100; // year
chip_done();
return(calc_time_t(&tm));
}
unsigned long
rtc_time_hy7201()
{
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "hy7201", 0);
/*
* Read counter register.
*/
return in32(HY7201_RTC_BASE + HY7201_RTC_RTCDR);
}
unsigned long
rtc_time_primecell(unsigned base)
{
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "primecell", 0);
hwi_add_location(base, PRIMECELL_RTC_SIZE, 0, hwi_find_as(base, 1));
/*
* Read counter register.
* The manual says the RTSR interrupts bits are cleared on reset.
*/
return in32(base + PRIMECELL_RTC_DR);
}
void
hwi_add_rtc(const char *name, paddr_t base, unsigned reg_shift, unsigned len,
int mmap, int cent_reg) {
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, name, 0);
hwi_add_location(base, len << reg_shift, reg_shift, hwi_find_as(base, mmap));
if(cent_reg != -1) {
hwi_tag *cent = hwi_alloc_tag(HWI_TAG_INFO(regname));
cent->regname.regname = 0;
cent->regname.offset = cent_reg;
}
}
unsigned long
rtc_time_hy7201()
{
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "hy7201", 0);
/*
* FIXME: do we need to clear the match interrupt enables?
* do we need to set the clock divider?
*/
/*
* Read counter register.
*/
return in32(HY7201_RTC_BASE + HY7201_RTC_RTCDR);
}
unsigned long
rtc_time_pxa250(unsigned rttr)
{
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "pxa250", 0);
/*
* Set the RTTR if necessary.
* The h/w reset default is for a perfect 32.768KHz crystal.
*/
if (rttr != 0) {
out32(PXA250_RTC_BASE + PXA250_RTTR, rttr);
}
/*
* Read counter register.
* The manual says the RTSR interrupts bits are cleared on reset.
*/
return in32(PXA250_RTC_BASE + PXA250_RCNR);
}
unsigned long
rtc_time_sa1100(unsigned rttr)
{
unsigned tmp;
hwi_add_device(HWI_ITEM_BUS_UNKNOWN, HWI_ITEM_DEVCLASS_RTC, "sa1100", 0);
/*
* FIXME: disable the RTC and 1HZ interrupts?
* According to the manual, these are undefined on reset
*/
out32(SA1100_RTC_BASE + SA1100_RTSR, 0);
/*
* Check if the IPL has set the RTTR.
*/
tmp = in32(SA1100_RTC_BASE + SA1100_RTTR);
if (tmp == 0) {
/*
* RTTR is not set - the RTC has been clocked at 32.768KHz since
* the reset, so the time read below is going to very wrong...
*/
if (rttr == 0) {
/*
* Set default value for perfect 32.768KHz crystal
*/
rttr = 0x7fff;
}
out32(SA1100_RTC_BASE + SA1100_RTTR, rttr);
}
/*
* Read counter register
*/
return in32(SA1100_RTC_BASE + SA1100_RCNR);
}
