static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) { const char *mode_str, *fp_str = ""; u32 comp_param1; u32 sda_falling_time, scl_falling_time; struct i2c_timings *t = &dev->timings; u32 ic_clk; int ret; ret = i2c_dw_acquire_lock(dev); if (ret) return ret; comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1); i2c_dw_release_lock(dev); /* Set standard and fast speed dividers for high/low periods */ sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ /* Calculate SCL timing parameters for standard mode if not set */ if (!dev->ss_hcnt || !dev->ss_lcnt) { ic_clk = i2c_dw_clk_rate(dev); dev->ss_hcnt = i2c_dw_scl_hcnt(ic_clk, 4000, /* tHD;STA = tHIGH = 4.0 us */ sda_falling_time, 0, /* 0: DW default, 1: Ideal */ 0); /* No offset */ dev->ss_lcnt = i2c_dw_scl_lcnt(ic_clk, 4700, /* tLOW = 4.7 us */ scl_falling_time, 0); /* No offset */ } dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", dev->ss_hcnt, dev->ss_lcnt); /* * Set SCL timing parameters for fast mode or fast mode plus. Only * difference is the timing parameter values since the registers are * the same. */ if (t->bus_freq_hz == 1000000) { /* * Check are fast mode plus parameters available and use * fast mode if not. */ if (dev->fp_hcnt && dev->fp_lcnt) { dev->fs_hcnt = dev->fp_hcnt; dev->fs_lcnt = dev->fp_lcnt; fp_str = " Plus"; } } /* * Calculate SCL timing parameters for fast mode if not set. They are * needed also in high speed mode. */ if (!dev->fs_hcnt || !dev->fs_lcnt) { ic_clk = i2c_dw_clk_rate(dev); dev->fs_hcnt = i2c_dw_scl_hcnt(ic_clk, 600, /* tHD;STA = tHIGH = 0.6 us */ sda_falling_time, 0, /* 0: DW default, 1: Ideal */ 0); /* No offset */ dev->fs_lcnt = i2c_dw_scl_lcnt(ic_clk, 1300, /* tLOW = 1.3 us */ scl_falling_time, 0); /* No offset */ } dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", fp_str, dev->fs_hcnt, dev->fs_lcnt); /* Check is high speed possible and fall back to fast mode if not */ if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == DW_IC_CON_SPEED_HIGH) { if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { dev_err(dev->dev, "High Speed not supported!\n"); dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; dev->master_cfg |= DW_IC_CON_SPEED_FAST; dev->hs_hcnt = 0; dev->hs_lcnt = 0; } else if (dev->hs_hcnt && dev->hs_lcnt) { dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", dev->hs_hcnt, dev->hs_lcnt); } } ret = i2c_dw_set_sda_hold(dev); if (ret) goto out; switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) { case DW_IC_CON_SPEED_STD: mode_str = "Standard Mode"; break; case DW_IC_CON_SPEED_HIGH: mode_str = "High Speed Mode"; break; default: mode_str = "Fast Mode"; } dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str); out: return ret; }
/** * i2c_dw_init() - initialize the designware i2c master hardware * @dev: device private data * * This functions configures and enables the I2C master. * This function is called during I2C init function, and in case of timeout at * run time. */ int i2c_dw_init(struct dw_i2c_dev *dev) { u32 input_clock_khz; u32 hcnt, lcnt; u32 reg; u32 cycle; input_clock_khz = dev->get_clk_rate_khz(dev); /* Configure register endianess access */ reg = dw_readl(dev, DW_IC_COMP_TYPE); if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { dev->swab = 1; reg = DW_IC_COMP_TYPE_VALUE; } if (reg != DW_IC_COMP_TYPE_VALUE) { dev_err(dev->dev, "Unknown Synopsys component type: " "0x%08x\n", reg); return -ENODEV; } /* Disable the adapter */ dw_writel(dev, 0, DW_IC_ENABLE); /* set standard and fast speed deviders for high/low periods */ /* Standard-mode */ hcnt = i2c_dw_scl_hcnt(input_clock_khz, 40, /* tHD;STA = tHIGH = 4.0 us */ 8, /* tf = 0.3 us */ 0, /* 0: DW default, 1: Ideal */ 0); /* No offset */ lcnt = i2c_dw_scl_lcnt(input_clock_khz, 47, /* tLOW = 4.7 us */ 6, /* tf = 0.3 us */ 0); /* No offset */ dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); /* Fast-mode */ hcnt = i2c_dw_scl_hcnt(input_clock_khz, 6, /* tHD;STA = tHIGH = 0.6 us */ 3, /* tf = 0.3 us */ 0, /* 0: DW default, 1: Ideal */ 0); /* No offset */ lcnt = i2c_dw_scl_lcnt(input_clock_khz, 13, /* tLOW = 1.3 us */ 3, /* tf = 0.3 us */ 0); /* No offset */ dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); /* Configure Tx/Rx FIFO threshold levels */ dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); dw_writel(dev, 0, DW_IC_RX_TL); /* Calculate cycle time, the unit is ns */ cycle = 1000000 / input_clock_khz; /* Set sda hold time as 200 ns */ dw_writel(dev, 200/cycle, DW_IC_SDA_HOLD); /* configure the i2c master */ dw_writel(dev, dev->master_cfg , DW_IC_CON); return 0; }