/*
* Internal simplified write function:
* i2c_regs: Pointer to I2C registers for current bus
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one register)
* data: Where to read the data
* len: How many bytes to write
*
* Returns: 0 on success, not 0 on failure
*/
static int __i2c_write(struct u5500_i2c_regs *i2c_regs, u8 chip, uint addr,
int alen, u8 *data, int len)
{
int i;
u32 mcr = 0;
/* Set the address mode to 7 bit */
WRITE_FIELD(mcr, I2C_MCR_AM, I2C_MCR_SHIFT_AM, 1);
/* Store the slave address in the master control register */
WRITE_FIELD(mcr, I2C_MCR_A7, I2C_MCR_SHIFT_A7, chip);
/* Write operation */
CLR_BIT(mcr, I2C_MCR_OP);
/* Current transaction is terminated by STOP condition */
SET_BIT(mcr, I2C_MCR_STOP);
/* Frame length: addr byte + len */
WRITE_FIELD(mcr, I2C_MCR_LENGTH, I2C_MCR_SHIFT_LENGTH, (alen + len));
/* Write MCR register */
writel(mcr, &i2c_regs->mcr);
if (i2c_write_addr(i2c_regs, addr, alen) != 0)
return -1;
for (i = 0; i < len; i++) {
/* Wait until the Tx FIFO is not full */
if (loop_till_bit_clear((void *)&i2c_regs->risr,
I2C_INT_TXFF, I2C_ENDAD_COUNTER))
return -1;
/* it is a 32 bit register with upper 24 reserved R/O */
writeb(data[i], &i2c_regs->tfr);
}
/* Check for Master Transaction Done */
if (loop_till_bit_set((void *)&i2c_regs->risr, I2C_INT_MTD,
I2C_ENDAD_COUNTER)) {
printf("i2c_write_byte error2: risr %08x\n",
i2c_regs->risr);
return -1;
}
/* Acknowledge Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTD);
/* Acknowledge Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTDWS);
return 0;
}
/*
* flush_fifo - flush the I2C TX and RX FIFOs
*/
static void flush_fifo(struct u5500_i2c_regs *i2c_regs)
{
int counter = I2C_FIFO_FLUSH_COUNTER;
/* Flush Tx FIFO */
i2c_set_bit(&i2c_regs->cr, I2C_CR_FTX);
/* Flush Rx FIFO */
i2c_set_bit(&i2c_regs->cr, I2C_CR_FRX);
while (counter--) {
if (!(readl(&i2c_regs->cr) & (I2C_CR_FTX | I2C_CR_FRX)))
break;
}
return;
}
/*
* i2c_abort - called when a I2C transaction failed
*/
static void i2c_abort(struct u5500_i2c_regs *i2c_regs)
{
#ifdef DEBUG
print_abort_reason(i2c_regs);
#endif
/* flush RX and TX fifos */
flush_fifo(i2c_regs);
/* Acknowledge the Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTD);
/* Acknowledge the Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTDWS);
i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
}
/**
* write_i2c() - Write data to I2C client.
* @dev: private data of I2C Driver
*
* This function writes data to I2C client
*/
static int write_i2c(struct nmk_i2c_dev *dev)
{
u32 status = 0;
u32 mcr;
u32 irq_mask = 0;
int timeout;
mcr = load_i2c_mcr_reg(dev);
writel(mcr, dev->virtbase + I2C_MCR);
/* load the current CR value */
writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
dev->virtbase + I2C_CR);
/* enable the controller */
i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
init_completion(&dev->xfer_complete);
/* enable interrupts by settings the masks */
irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
I2C_IT_MAL | I2C_IT_BERR);
/*
* check if we want to transfer a single or multiple bytes, if so
* set the MTDWS bit (Master Transaction Done Without Stop)
* to start repeated start operation
*/
if (dev->stop)
irq_mask |= I2C_IT_MTD;
else
irq_mask |= I2C_IT_MTDWS;
irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
dev->virtbase + I2C_IMSCR);
timeout = wait_for_completion_interruptible_timeout(
&dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
if (timeout < 0) {
dev_err(&dev->pdev->dev,
"wait_for_completion_interruptible_timeout"
"returned %d waiting for event\n", timeout);
status = timeout;
}
if (timeout == 0) {
/* controler has timedout, re-init the h/w */
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
(void) init_hw(dev);
status = -ETIMEDOUT;
}
return status;
}
/*
* Probe the given I2C chip address. Returns 0 if a chip responded,
* not 0 on failure.
*/
int i2c_probe(uchar chip)
{
u32 mcr = 0;
struct u5500_i2c_regs *i2c_regs;
if (chip == CONFIG_SYS_I2C_SLAVE)
return 1;
i2c_regs = i2c_dev[i2c_bus_num];
/* Set the address mode to 7 bit */
WRITE_FIELD(mcr, I2C_MCR_AM, I2C_MCR_SHIFT_AM, 1);
/* Store the slave address in the master control register */
WRITE_FIELD(mcr, I2C_MCR_A10, I2C_MCR_SHIFT_A7, chip);
/* Read operation */
SET_BIT(mcr, I2C_MCR_OP);
/* Set the frame length to one byte */
WRITE_FIELD(mcr, I2C_MCR_LENGTH, I2C_MCR_SHIFT_LENGTH, 1);
/* Current transaction is terminated by STOP condition */
SET_BIT(mcr, I2C_MCR_STOP);
/* Write MCR register */
writel(mcr, &i2c_regs->mcr);
/* Wait until the Rx Fifo is not empty */
if (loop_till_bit_clear((void *)&i2c_regs->risr, I2C_INT_RXFE,
I2C_ENDAD_COUNTER)) {
i2c_abort(i2c_regs);
return -1;
}
flush_fifo(i2c_regs);
/* Acknowledge the Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTD);
/* Acknowledge the Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTDWS);
return 0;
}
/*
* i2c_init - initialize the i2c bus
*
* speed: bus speed (in HZ)
* slaveaddr: address of device in slave mode
*
* Slave mode is not implemented.
*/
void i2c_init(int speed, int slaveaddr)
{
struct u5500_i2c_regs *i2c_regs;
debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
u5500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
i2c_clock_bits[i2c_bus_num].pcken,
i2c_clock_bits[i2c_bus_num].kcken);
i2c_regs = i2c_dev[i2c_bus_num];
/* Disable the controller */
i2c_clr_bit(&i2c_regs->cr, I2C_CR_PE);
/* Clear registers */
writel(0, &i2c_regs->cr);
writel(0, &i2c_regs->scr);
writel(0, &i2c_regs->hsmcr);
writel(0, &i2c_regs->tftr);
writel(0, &i2c_regs->rftr);
writel(0, &i2c_regs->dmar);
i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
/*
* Set our own address.
* Set slave address mode to 7 bit addressing mode
*/
i2c_clr_bit(&i2c_regs->cr, I2C_CR_SAM);
i2c_write_field(&i2c_regs->scr, I2C_SCR_ADDR, I2C_SCR_SHIFT_ADDR,
slaveaddr);
/* Slave Data Set up Time */
i2c_write_field(&i2c_regs->scr, I2C_SCR_DATA_SETUP_TIME,
I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
/* Disable the DMA sync logic */
i2c_write_field(&i2c_regs->cr, I2C_CR_DMA_SLE,
I2C_CR_SHIFT_DMA_SLE, 0);
/* Disable interrupts */
writel(0, &i2c_regs->imscr);
/* Configure bus master mode */
i2c_write_field(&i2c_regs->cr, I2C_CR_OM, I2C_CR_SHIFT_OM,
I2C_BUS_MASTER_MODE);
/* Set FIFO threshold values */
writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
/* Enable the I2C Controller */
i2c_set_bit(&i2c_regs->cr, I2C_CR_PE);
bus_initialized[i2c_bus_num] = 1;
}
/**
* read_i2c() - Read from I2C client device
* @dev: private data of I2C Driver
*
* This function reads from i2c client device when controller is in
* master mode. There is a completion timeout. If there is no transfer
* before timeout error is returned.
*/
static int read_i2c(struct nmk_i2c_dev *dev)
{
u32 status = 0;
u32 mcr;
u32 irq_mask = 0;
int timeout;
mcr = load_i2c_mcr_reg(dev);
writel(mcr, dev->virtbase + I2C_MCR);
/* load the current CR value */
writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
dev->virtbase + I2C_CR);
/* enable the controller */
i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
init_completion(&dev->xfer_complete);
/* enable interrupts by setting the mask */
irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
I2C_IT_MAL | I2C_IT_BERR);
if (dev->stop)
irq_mask |= I2C_IT_MTD;
else
irq_mask |= I2C_IT_MTDWS;
irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
dev->virtbase + I2C_IMSCR);
timeout = wait_for_completion_interruptible_timeout(
&dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
if (timeout < 0) {
dev_err(&dev->pdev->dev,
"wait_for_completion_interruptible_timeout"
"returned %d waiting for event\n", timeout);
status = timeout;
}
if (timeout == 0) {
/* controler has timedout, re-init the h/w */
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
(void) init_hw(dev);
status = -ETIMEDOUT;
}
return status;
}
/*
* Internal simplified read function:
* i2c_regs: Pointer to I2C registers for current bus
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one register)
* value: Where to put the data
*
* Returns: 0 on success, not 0 on failure
*/
static int i2c_read_byte(struct u5500_i2c_regs *i2c_regs, uchar chip,
uint addr, int alen, uchar *value)
{
u32 mcr = 0;
/* Set the address mode to 7 bit */
WRITE_FIELD(mcr, I2C_MCR_AM, I2C_MCR_SHIFT_AM, 1);
/* Store the slave address in the master control register */
WRITE_FIELD(mcr, I2C_MCR_A7, I2C_MCR_SHIFT_A7, chip);
if (alen != 0) {
/* Master write operation */
CLR_BIT(mcr, I2C_MCR_OP);
/* Configure the Frame length to one byte */
WRITE_FIELD(mcr, I2C_MCR_LENGTH, I2C_MCR_SHIFT_LENGTH, 1);
/* Repeated start, no stop */
CLR_BIT(mcr, I2C_MCR_STOP);
/* Write Master Control Register */
writel(mcr, &i2c_regs->mcr);
/* send addr/index */
if (i2c_write_addr(i2c_regs, addr, alen) != 0)
return -1;
/* Check for the Master Transaction Done Without Stop */
if (loop_till_bit_set((void *)&i2c_regs->risr,
I2C_INT_MTDWS, I2C_ENDAD_COUNTER)) {
return -1;
}
/* Acknowledge the Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTDWS);
}
/* Master control configuration for read operation */
SET_BIT(mcr, I2C_MCR_OP);
/* Configure the STOP condition, we read only one byte */
SET_BIT(mcr, I2C_MCR_STOP);
/* Set the frame length to one byte, we support only 1 byte reads */
WRITE_FIELD(mcr, I2C_MCR_LENGTH, I2C_MCR_SHIFT_LENGTH, 1);
i2c_write_field(&i2c_regs->mcr, I2C_MCR_LENGTH_STOP_OP,
I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
/*
* receive_data_polling
*/
/* Wait until the Rx FIFO is not empty */
if (loop_till_bit_clear((void *)&i2c_regs->risr, I2C_INT_RXFE,
I2C_ENDAD_COUNTER))
return -1;
/* Read the data byte from Rx FIFO */
*value = readb(&i2c_regs->rfr);
/* Wait until the work is done */
if (loop_till_bit_set((void *)&i2c_regs->risr, I2C_INT_MTD,
I2C_ENDAD_COUNTER))
return -1;
/* Acknowledge the Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTD);
/* If MTD is set, Master Transaction Done Without Stop is set too */
i2c_set_bit(&i2c_regs->icr, I2C_INT_MTDWS);
return 0;
}
