static int cpu_set(struct drm_i915_gem_object *obj, unsigned long offset, u32 v) { unsigned int needs_clflush; struct page *page; u32 *map; int err; err = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); if (err) return err; page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); if (needs_clflush & CLFLUSH_BEFORE) clflush(map+offset_in_page(offset) / sizeof(*map)); map[offset_in_page(offset) / sizeof(*map)] = v; if (needs_clflush & CLFLUSH_AFTER) clflush(map+offset_in_page(offset) / sizeof(*map)); kunmap_atomic(map); i915_gem_obj_finish_shmem_access(obj); return 0; }
static int render_state_setup(struct intel_render_state *so, struct drm_i915_private *i915) { const struct intel_renderstate_rodata *rodata = so->rodata; struct drm_i915_gem_object *obj = so->vma->obj; unsigned int i = 0, reloc_index = 0; unsigned int needs_clflush; u32 *d; int ret; ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); if (ret) return ret; d = kmap_atomic(i915_gem_object_get_dirty_page(obj, 0)); while (i < rodata->batch_items) { u32 s = rodata->batch[i]; if (i * 4 == rodata->reloc[reloc_index]) { u64 r = s + so->vma->node.start; s = lower_32_bits(r); if (HAS_64BIT_RELOC(i915)) { if (i + 1 >= rodata->batch_items || rodata->batch[i + 1] != 0) goto err; d[i++] = s; s = upper_32_bits(r); } reloc_index++; } d[i++] = s; } if (rodata->reloc[reloc_index] != -1) { DRM_ERROR("only %d relocs resolved\n", reloc_index); goto err; } so->batch_offset = so->vma->node.start; so->batch_size = rodata->batch_items * sizeof(u32); while (i % CACHELINE_DWORDS) OUT_BATCH(d, i, MI_NOOP); so->aux_offset = i * sizeof(u32); if (HAS_POOLED_EU(i915)) { /* * We always program 3x6 pool config but depending upon which * subslice is disabled HW drops down to appropriate config * shown below. * * In the below table 2x6 config always refers to * fused-down version, native 2x6 is not available and can * be ignored * * SNo subslices config eu pool configuration * ----------------------------------------------------------- * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) * 2 ss0 disabled (2x6) - 0x00777000 (3+9) * 3 ss1 disabled (2x6) - 0x00770000 (6+6) * 4 ss2 disabled (2x6) - 0x00007000 (9+3) */ u32 eu_pool_config = 0x00777000; OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); OUT_BATCH(d, i, eu_pool_config); OUT_BATCH(d, i, 0); OUT_BATCH(d, i, 0); OUT_BATCH(d, i, 0); } OUT_BATCH(d, i, MI_BATCH_BUFFER_END); so->aux_size = i * sizeof(u32) - so->aux_offset; so->aux_offset += so->batch_offset; /* * Since we are sending length, we need to strictly conform to * all requirements. For Gen2 this must be a multiple of 8. */ so->aux_size = ALIGN(so->aux_size, 8); if (needs_clflush) drm_clflush_virt_range(d, i * sizeof(u32)); kunmap_atomic(d); ret = i915_gem_object_set_to_gtt_domain(obj, false); out: i915_gem_obj_finish_shmem_access(obj); return ret; err: kunmap_atomic(d); ret = -EINVAL; goto out; }