void vBSP430platformInitialize_ni (void)
{
int crystal_ok = 0;
(void)crystal_ok;
#if BSP430_PLATFORM_BOOT_DISABLE_WATCHDOG - 0
/* Hold off watchdog */
WDTCTL = WDTPW | WDTHOLD;
#endif /* configBSP430_CORE_SUPPORT_WATCHDOG */
#if (BSP430_PLATFORM_BOOT_CONFIGURE_LEDS - 0) && (BSP430_LED - 0)
vBSP430ledInitialize_ni();
#endif /* BSP430_PLATFORM_BOOT_CONFIGURE_LEDS */
#if BSP430_PLATFORM_BOOT_CONFIGURE_LFXT1 - 0
/* Enable XT1 functions and clock */
crystal_ok = iBSP430clockConfigureLFXT1_ni(1, (BSP430_PLATFORM_BOOT_LFXT1_DELAY_SEC * BSP430_CLOCK_PUC_MCLK_HZ) / BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES);
#endif /* BSP430_PLATFORM_BOOT_CONFIGURE_LFXT1 */
#if BSP430_PLATFORM_BOOT_CONFIGURE_CLOCKS - 0
iBSP430clockConfigureACLK_ni(BSP430_PLATFORM_BOOT_ACLKSRC);
ulBSP430clockConfigureMCLK_ni(BSP430_CLOCK_NOMINAL_MCLK_HZ);
iBSP430clockConfigureSMCLKDividingShift_ni(BSP430_CLOCK_NOMINAL_SMCLK_DIVIDING_SHIFT);
#if configBSP430_CORE_DISABLE_FLL - 0
__bis_status_register(SCG0);
#endif /* configBSP430_CORE_DISABLE_FLL */
#endif /* BSP430_PLATFORM_BOOT_CONFIGURE_CLOCKS */
#if BSP430_UPTIME - 0
vBSP430uptimeStart_ni();
#endif /* BSP430_UPTIME */
}
int
iBSP430bc2TrimToMCLK_ni (unsigned long mclk_Hz)
{
volatile sBSP430hplTIMER * tp = xBSP430hplLookupTIMER(BSP430_TIMER_CCACLK_PERIPH_HANDLE);
const int MAX_ITERATIONS = 16 * 256;
int rv = -1;
unsigned long aclk_Hz;
int iter = 0;
const int SAMPLE_PERIOD_ACLK = 10;
unsigned char bcsctl3;
unsigned int target_tsp;
if (! tp) {
return -1;
}
bcsctl3 = BCSCTL3;
if (0 != iBSP430clockConfigureACLK_ni(eBSP430clockSRC_XT1CLK_OR_VLOCLK)) {
return -1;
}
aclk_Hz = ulBSP430clockACLK_Hz_ni();
target_tsp = (SAMPLE_PERIOD_ACLK * mclk_Hz) / aclk_Hz;
tp->ctl = TASSEL_2 | MC_2 | TACLR;
/* SELM = DCOCLK; DIVM = /1 */
BCSCTL2 &= ~(SELM_MASK | DIVM_MASK);
while (iter++ < MAX_ITERATIONS) {
unsigned int freq_tsp;
freq_tsp = uiBSP430timerCaptureDelta_ni(BSP430_TIMER_CCACLK_PERIPH_HANDLE,
BSP430_TIMER_CCACLK_ACLK_CCIDX,
CM_2,
BSP430_TIMER_CCACLK_ACLK_CCIS,
SAMPLE_PERIOD_ACLK);
if (freq_tsp == target_tsp) {
configuredMCLK_Hz = mclk_Hz;
rv = 0;
break;
}
if (target_tsp < freq_tsp) {
/* DCO too fast. Decrement modulator; if underflowed,
* decrement RSEL */
if (0xFF == --DCOCTL) {
--BCSCTL1;
}
} else {
/* DCO too slow. Increment modulator; if overflowed,
* increment RSEL */
if (0 == ++DCOCTL) {
++BCSCTL1;
}
}
}
tp->ctl = 0;
BCSCTL3 = bcsctl3;
return rv;
}