static void __init
yosemite_setup_arch(void)
{
yosemite_set_emacdata();
ibm440gx_get_clocks(&clocks, YOSEMITE_SYSCLK, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
yosemite_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
yosemite_early_serial_map();
/* Identify the system */
printk( "AMCC PowerPC " BOARDNAME " Platform\n" );
}
static void __init sequoia_setup_arch(void)
{
sequoia_set_emacdata();
/* parm1 = sys clock is OK , parm 2 ser_clock to be checked */
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
sequoia_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else {
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
}
#endif
sequoia_early_serial_map();
printk( "AMCC PowerPC Sequoia platform\n" );
}
static void __init
yosemite_setup_arch(void)
{
uint32_t* gpio_base;
/* configuring GPIO1 for external interrupts */
gpio_base = (uint32_t*)ioremap64(PPC440EP_GPIO1_ADDR,
PPC440EP_GPIO_SIZE);
if (gpio_base) {
/* GPIO1_TCR reset bits 8-16*/
gpio_base[1] &= 0xff007fff;
/* GPIO1_TSRL reset bits 16-31*/
gpio_base[4] &= 0xffff0000;
/* GPIO1_ISR1L set bit pairs 16-17 to 30-31 to 01b*/
gpio_base[12] |= 0x5555;
/* GPIO1_TSRH reset bits 0-1*/
gpio_base[5] &= 0x3fffffff;
/* GPIO1_ISR1H set bit pair 0-1 to 01b*/
gpio_base[13] |= 0x40000000;
iounmap(gpio_base);
}
/* setting esxternal clk source for serial ports */
SDR_WRITE(DCRN_SDR_UART0, 0x800001);
SDR_WRITE(DCRN_SDR_UART1, 0x800001);
yosemite_set_emacdata();
ibm440gx_get_clocks(&clocks, YOSEMITE_SYSCLK, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
yosemite_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
yosemite_early_serial_map();
/* Identify the system */
printk( "AMCC PowerPC " BOARDNAME " Platform\n" );
}
static void __init
ocotea_setup_arch(void)
{
ocotea_set_emacdata();
ibm440gx_tah_enable();
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ocotea_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
static void __init
yucca_setup_arch(void)
{
yucca_set_emacdata();
#if !defined(CONFIG_BDI_SWITCH)
/*
* The Abatron BDI JTAG debugger does not tolerate others
* mucking with the debug registers.
*/
mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
#endif
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
/* 440GX and 440SPe clocking is the same - rd */
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCIXn host bridges */
yucca_setup_hoses();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
yucca_early_serial_map();
/* Identify the system */
printk("Yucca port (Roland Dreier <*****@*****.**>)\n");
}
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/*
* If we were passed in a board information, copy it into the
* residual data area.
*/
if (r3)
__res = *(bd_t *)(r3 + KERNELBASE);
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
ibm44x_platform_init();
ppc_md.setup_arch = ocotea_setup_arch;
ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
ppc_md.calibrate_decr = ocotea_calibrate_decr;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
#ifdef CONFIG_KGDB
ppc_md.early_serial_map = ocotea_early_serial_map;
#endif
ppc_md.init = ocotea_init;
}
static void __init
bamboo_setup_arch(void)
{
bamboo_set_emacdata();
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
bamboo_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
bamboo_early_serial_map();
/* Identify the system */
printk("IBM Bamboo port (MontaVista Software, Inc. ([email protected]))\n");
}
static void __init
taishan_setup_arch(void)
{
taishan_set_emacdata();
ibm440gx_tah_enable();
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
taishan_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
taishan_early_serial_map();
/* Identify the system */
printk("AMCC PowerPC 440GX Taishan Platform\n");
}
static void __init
luan_setup_arch(void)
{
luan_set_emacdata();
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
/* 440GX and 440SP clocking is the same -mdp */
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCIXn host bridges */
luan_setup_hoses();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
luan_early_serial_map();
/* Identify the system */
printk("Luan port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
