static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) { struct irq_desc *desc = irq_desc + irq; uint16_t intassign0, intassign1; unsigned int pin; pin = SYSINT1_IRQ_TO_PIN(irq); spin_lock_irq(&desc->lock); intassign0 = icu1_read(INTASSIGN0); intassign1 = icu1_read(INTASSIGN1); switch (pin) { case 0: intassign0 &= ~INTASSIGN_MASK; intassign0 |= (uint16_t)assign; break; case 1: intassign0 &= ~(INTASSIGN_MASK << 3); intassign0 |= (uint16_t)assign << 3; break; case 2: intassign0 &= ~(INTASSIGN_MASK << 6); intassign0 |= (uint16_t)assign << 6; break; case 3: intassign0 &= ~(INTASSIGN_MASK << 9); intassign0 |= (uint16_t)assign << 9; break; case 8: intassign0 &= ~(INTASSIGN_MASK << 12); intassign0 |= (uint16_t)assign << 12; break; case 9: intassign1 &= ~INTASSIGN_MASK; intassign1 |= (uint16_t)assign; break; case 11: intassign1 &= ~(INTASSIGN_MASK << 6); intassign1 |= (uint16_t)assign << 6; break; case 12: intassign1 &= ~(INTASSIGN_MASK << 9); intassign1 |= (uint16_t)assign << 9; break; default: spin_unlock_irq(&desc->lock); return -EINVAL; } sysint1_assign[pin] = assign; icu1_write(INTASSIGN0, intassign0); icu1_write(INTASSIGN1, intassign1); spin_unlock_irq(&desc->lock); return 0; }
static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear) { uint16_t data; data = icu1_read(offset); data &= ~clear; icu1_write(offset, data); return data; }
static inline uint16_t icu1_set(uint8_t offset, uint16_t set) { uint16_t data; data = icu1_read(offset); data |= set; icu1_write(offset, data); return data; }
static int __init vr41xx_icu_init(void) { unsigned long icu1_start, icu2_start; int i; switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: icu1_start = ICU1_TYPE1_BASE; icu2_start = ICU2_TYPE1_BASE; break; case CPU_VR4122: case CPU_VR4131: case CPU_VR4133: icu1_start = ICU1_TYPE2_BASE; icu2_start = ICU2_TYPE2_BASE; break; default: printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n"); return -ENODEV; } if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL) return -EBUSY; if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) { release_mem_region(icu1_start, ICU1_SIZE); return -EBUSY; } icu1_base = ioremap(icu1_start, ICU1_SIZE); if (icu1_base == NULL) { release_mem_region(icu1_start, ICU1_SIZE); release_mem_region(icu2_start, ICU2_SIZE); return -ENOMEM; } icu2_base = ioremap(icu2_start, ICU2_SIZE); if (icu2_base == NULL) { iounmap(icu1_base); release_mem_region(icu1_start, ICU1_SIZE); release_mem_region(icu2_start, ICU2_SIZE); return -ENOMEM; } icu1_write(MSYSINT1REG, 0); icu1_write(MGIUINTLREG, 0xffff); icu2_write(MSYSINT2REG, 0); icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) irq_desc[i].chip = &sysint1_irq_type; for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) irq_desc[i].chip = &sysint2_irq_type; cascade_irq(INT0_IRQ, icu_get_irq); cascade_irq(INT1_IRQ, icu_get_irq); cascade_irq(INT2_IRQ, icu_get_irq); cascade_irq(INT3_IRQ, icu_get_irq); cascade_irq(INT4_IRQ, icu_get_irq); return 0; }
static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) { struct irq_desc *desc = irq_desc + irq; uint16_t intassign2, intassign3; unsigned int pin; pin = SYSINT2_IRQ_TO_PIN(irq); spin_lock_irq(&desc->lock); intassign2 = icu1_read(INTASSIGN2); intassign3 = icu1_read(INTASSIGN3); switch (pin) { case 0: intassign2 &= ~INTASSIGN_MASK; intassign2 |= (uint16_t)assign; break; case 1: intassign2 &= ~(INTASSIGN_MASK << 3); intassign2 |= (uint16_t)assign << 3; break; case 3: intassign2 &= ~(INTASSIGN_MASK << 6); intassign2 |= (uint16_t)assign << 6; break; case 4: intassign2 &= ~(INTASSIGN_MASK << 9); intassign2 |= (uint16_t)assign << 9; break; case 5: intassign2 &= ~(INTASSIGN_MASK << 12); intassign2 |= (uint16_t)assign << 12; break; case 6: intassign3 &= ~INTASSIGN_MASK; intassign3 |= (uint16_t)assign; break; case 7: intassign3 &= ~(INTASSIGN_MASK << 3); intassign3 |= (uint16_t)assign << 3; break; case 8: intassign3 &= ~(INTASSIGN_MASK << 6); intassign3 |= (uint16_t)assign << 6; break; case 9: intassign3 &= ~(INTASSIGN_MASK << 9); intassign3 |= (uint16_t)assign << 9; break; case 10: intassign3 &= ~(INTASSIGN_MASK << 12); intassign3 |= (uint16_t)assign << 12; break; default: return -EINVAL; } sysint2_assign[pin] = assign; icu1_write(INTASSIGN2, intassign2); icu1_write(INTASSIGN3, intassign3); spin_unlock_irq(&desc->lock); return 0; }