static void sis_85c471_write(uint16_t port, uint8_t val, void *priv) { sis_85c471_t *dev = (sis_85c471_t *) priv; uint8_t index = (port & 1) ? 0 : 1; uint8_t valxor; if (index) { if ((val >= 0x50) && (val <= 0x76)) dev->cur_reg = val; return; } else { if ((dev->cur_reg < 0x50) || (dev->cur_reg > 0x76)) return; valxor = val ^ dev->regs[dev->cur_reg - 0x50]; /* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */ if (dev->cur_reg != 0x52) dev->regs[dev->cur_reg - 0x50] = val; } switch(dev->cur_reg) { case 0x73: if (valxor & 0x40) { ide_pri_disable(); if (val & 0x40) ide_pri_enable(); } if (valxor & 0x20) { serial_remove(dev->uart[0]); serial_remove(dev->uart[1]); if (val & 0x20) { serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ); serial_setup(dev->uart[0], SERIAL2_ADDR, SERIAL2_IRQ); } } if (valxor & 0x10) { lpt1_remove(); if (val & 0x10) lpt1_init(0x378); } break; } dev->cur_reg = 0; }
void piix_write(int func, int addr, uint8_t val, void *priv) { // pclog("piix_write: func=%d addr=%02x val=%02x %04x:%08x\n", func, addr, val, CS, pc); if (func > 1) return; if (func == 1) /*IDE*/ { switch (addr) { case 0x04: card_piix_ide[0x04] = (card_piix_ide[0x04] & ~5) | (val & 5); break; case 0x07: card_piix_ide[0x07] = (card_piix_ide[0x07] & ~0x38) | (val & 0x38); break; case 0x0d: card_piix_ide[0x0d] = val; break; case 0x20: card_piix_ide[0x20] = (val & ~0x0f) | 1; break; case 0x21: card_piix_ide[0x21] = val; break; case 0x40: card_piix_ide[0x40] = val; break; case 0x41: if ((val ^ card_piix_ide[0x41]) & 0x80) { ide_pri_disable(); if (val & 0x80) ide_pri_enable(); } card_piix_ide[0x41] = val; break; case 0x42: card_piix_ide[0x42] = val; break; case 0x43: if ((val ^ card_piix_ide[0x43]) & 0x80) { ide_sec_disable(); if (val & 0x80) ide_sec_enable(); } card_piix_ide[0x43] = val; break; } if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/ { uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8); io_removehandler(0, 0x10000, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL); if (card_piix_ide[0x04] & 1) io_sethandler(base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL); } // pclog("PIIX write %02X %02X\n", addr, val); } else { switch (addr) { case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0e: return; } card_piix[addr] = val; } }
void piix_write(int func, int addr, uint8_t val, void *priv) { // pclog("piix_write: func=%d addr=%02x val=%02x %04x:%08x\n", func, addr, val, CS, pc); if (func > 1) return; if (func == 1) /*IDE*/ { switch (addr) { case 0x04: // pclog("IDE on/off\n"); if (romset == ROM_P55T2P4) resetide(); card_piix_ide[0x04] = (card_piix_ide[0x04] & ~5) | (val & 5); break; case 0x07: card_piix_ide[0x07] = (card_piix_ide[0x07] & ~0x38) | (val & 0x38); break; case 0x0d: card_piix_ide[0x0d] = val; break; case 0x20: card_piix_ide[0x20] = (val & ~0x0f) | 1; break; case 0x21: card_piix_ide[0x21] = val; break; #if 0 case 0x33: /* Note by OBattler: This is a hack, but it's needed to reset the cylinders of the IDE devices. */ if (romset != ROM_P55T2P4) break; if (val != piix_33) { resetide(); } piix_33 = val; break; #endif case 0x40: card_piix_ide[0x40] = val; break; case 0x41: if ((val ^ card_piix_ide[0x41]) & 0x80) { ide_pri_disable(); if (val & 0x80) ide_pri_enable(); } card_piix_ide[0x41] = val; break; case 0x42: card_piix_ide[0x42] = val; break; case 0x43: if ((val ^ card_piix_ide[0x43]) & 0x80) { ide_sec_disable(); if (val & 0x80) ide_sec_enable(); } card_piix_ide[0x43] = val; break; case 0x44: if (piix_type >= 3) card_piix_ide[0x44] = val; break; } if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/ { uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8); io_removehandler(0, 0x10000, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL); if (card_piix_ide[0x04] & 1) io_sethandler(base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL); } // pclog("PIIX write %02X %02X\n", addr, val); } else { switch (addr) { case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0e: return; } if (addr == 0x6A) { if (piix_type == 1) card_piix[addr] = (val & 0xFC) | (card_piix[addr] | 3); else if (piix_type == 3) card_piix[addr] = (val & 0xFD) | (card_piix[addr] | 2); } else card_piix[addr] = val; } }
void sis85c471_write(uint16_t port, uint8_t val, void *priv) { uint8_t index = (port & 1) ? 0 : 1; int temp; uint8_t x; #ifndef RELEASE_BUILD pclog("sis85c471_write : port=%04x reg %02X = %02X\n", port, sis85c471_curreg, val); #endif if (index) { if ((val >= 0x50) && (val <= 0x76)) sis85c471_curreg = val; return; } else { if ((sis85c471_curreg < 0x50) || (sis85c471_curreg > 0x76)) return; x = val ^ sis85c471_regs[sis85c471_curreg - 0x50]; /* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */ if (sis85c471_curreg != 0x52) sis85c471_regs[sis85c471_curreg - 0x50] = val; goto process_value; } return; process_value: switch(sis85c471_curreg) { case 0x73: #if 0 if (x & 0x40) { if (val & 0x40) ide_pri_enable(); else ide_pri_disable(); } #endif if (x & 0x20) { if (val & 0x20) { serial1_init(0x3f8, 4); serial2_init(0x2f8, 3); mouse_serial_init(); } else { serial1_remove(); serial2_remove(); } } if (x & 0x10) { if (val & 0x10) lpt1_init(0x378); else lpt1_remove(); } break; } sis85c471_curreg = 0; }