static void test(data_t *data)
{
igt_output_t *output = data->output;
struct igt_fb *fb = &data->fb[1];
drmModeModeInfo *mode;
cairo_t *cr;
uint32_t caching;
void *buf;
igt_crc_t crc;
mode = igt_output_get_mode(output);
/* create a non-white fb where we can pwrite later */
igt_create_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE, fb);
cr = igt_get_cairo_ctx(data->drm_fd, fb);
igt_paint_test_pattern(cr, fb->width, fb->height);
cairo_destroy(cr);
/* flip to it to make it UC/WC and fully flushed */
drmModeSetPlane(data->drm_fd,
data->primary->drm_plane->plane_id,
output->config.crtc->crtc_id,
fb->fb_id, 0,
0, 0, fb->width, fb->height,
0, 0, fb->width << 16, fb->height << 16);
/* flip back the original white buffer */
drmModeSetPlane(data->drm_fd,
data->primary->drm_plane->plane_id,
output->config.crtc->crtc_id,
data->fb[0].fb_id, 0,
0, 0, fb->width, fb->height,
0, 0, fb->width << 16, fb->height << 16);
/* make sure caching mode has become UC/WT */
caching = gem_get_caching(data->drm_fd, fb->gem_handle);
igt_assert(caching == I915_CACHING_NONE || caching == I915_CACHING_DISPLAY);
/* use pwrite to make the other fb all white too */
buf = malloc(fb->size);
igt_assert(buf != NULL);
memset(buf, 0xff, fb->size);
gem_write(data->drm_fd, fb->gem_handle, 0, buf, fb->size);
free(buf);
/* and flip to it */
drmModeSetPlane(data->drm_fd,
data->primary->drm_plane->plane_id,
output->config.crtc->crtc_id,
fb->fb_id, 0,
0, 0, fb->width, fb->height,
0, 0, fb->width << 16, fb->height << 16);
/* check that the crc is as expected, which requires that caches got flushed */
igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
igt_assert_crc_equal(&crc, &data->ref_crc);
}
static void
paint_color(data_t *d, struct igt_fb *fb, uint16_t w, uint16_t h)
{
cairo_t *cr;
cr = igt_get_cairo_ctx(d->drm_fd, fb);
igt_paint_test_pattern(cr, w, h);
cairo_destroy(cr);
}
static void do_single_test(data_t *data, int x, int y)
{
igt_display_t *display = &data->display;
igt_pipe_crc_t *pipe_crc = data->pipe_crc;
igt_crc_t crc, ref_crc;
igt_plane_t *cursor;
cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb);
igt_print_activity();
/* Hardware test */
igt_paint_test_pattern(cr, data->screenw, data->screenh);
cursor_enable(data);
cursor = igt_output_get_plane(data->output, IGT_PLANE_CURSOR);
igt_plane_set_position(cursor, x, y);
igt_display_commit(display);
igt_wait_for_vblank(data->drm_fd, data->pipe);
igt_pipe_crc_collect_crc(pipe_crc, &crc);
if (data->flags & (TEST_DPMS | TEST_SUSPEND)) {
igt_crc_t crc_after;
if (data->flags & TEST_DPMS) {
igt_debug("dpms off/on cycle\n");
kmstest_set_connector_dpms(data->drm_fd,
data->output->config.connector,
DRM_MODE_DPMS_OFF);
kmstest_set_connector_dpms(data->drm_fd,
data->output->config.connector,
DRM_MODE_DPMS_ON);
}
if (data->flags & TEST_SUSPEND)
igt_system_suspend_autoresume();
igt_pipe_crc_collect_crc(pipe_crc, &crc_after);
igt_assert_crc_equal(&crc, &crc_after);
}
cursor_disable(data);
igt_display_commit(display);
/* Now render the same in software and collect crc */
draw_cursor(cr, x, y, data->curw, data->curh);
igt_display_commit(display);
igt_wait_for_vblank(data->drm_fd, data->pipe);
igt_pipe_crc_collect_crc(pipe_crc, &ref_crc);
/* Clear screen afterwards */
igt_assert_crc_equal(&crc, &ref_crc);
igt_paint_color(cr, 0, 0, data->screenw, data->screenh,
0.0, 0.0, 0.0);
}
static uint32_t create_fb(int drm_fd, int width, int height)
{
struct igt_fb fb;
cairo_t *cr;
uint32_t buffer_id;
buffer_id = igt_create_fb(drm_fd, width, height, DRM_FORMAT_XRGB8888,
LOCAL_DRM_FORMAT_MOD_NONE, &fb);
cr = igt_get_cairo_ctx(drm_fd, &fb);
igt_paint_test_pattern(cr, width, height);
cairo_destroy(cr);
return buffer_id;
}
static int paint_fb(struct igt_fb *fb, const char *test_name,
const char *mode_format_str, const char *cconf_str)
{
cairo_t *cr;
cr = igt_get_cairo_ctx(drm_fd, fb);
igt_paint_color_gradient(cr, 0, 0, fb->width, fb->height, 1, 1, 1);
igt_paint_test_pattern(cr, fb->width, fb->height);
cairo_move_to(cr, fb->width / 2, fb->height / 2);
cairo_set_font_size(cr, 36);
igt_cairo_printf_line(cr, align_hcenter, 10, "%s", test_name);
igt_cairo_printf_line(cr, align_hcenter, 10, "%s", mode_format_str);
igt_cairo_printf_line(cr, align_hcenter, 10, "%s", cconf_str);
cairo_destroy(cr);
return 0;
}
static void do_fail_test(data_t *data, int x, int y, int expect)
{
igt_display_t *display = &data->display;
igt_plane_t *cursor;
cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb);
int ret;
igt_print_activity();
/* Hardware test */
igt_paint_test_pattern(cr, data->screenw, data->screenh);
cursor_enable(data);
cursor = igt_output_get_plane(data->output, IGT_PLANE_CURSOR);
igt_plane_set_position(cursor, x, y);
ret = igt_display_try_commit2(display, COMMIT_LEGACY);
igt_plane_set_position(cursor, 0, 0);
cursor_disable(data);
igt_display_commit(display);
igt_assert_eq(ret, expect);
}
static void test(data_t *data)
{
igt_display_t *display = &data->display;
igt_output_t *output = data->output;
struct igt_fb *fb = &data->fb[1];
drmModeModeInfo *mode;
cairo_t *cr;
char *ptr;
uint32_t caching;
void *buf;
igt_crc_t crc;
mode = igt_output_get_mode(output);
/* create a non-white fb where we can write later */
igt_create_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE, fb);
ptr = dmabuf_mmap_framebuffer(data->drm_fd, fb);
cr = igt_get_cairo_ctx(data->drm_fd, fb);
igt_paint_test_pattern(cr, fb->width, fb->height);
cairo_destroy(cr);
/* flip to it to make it UC/WC and fully flushed */
igt_plane_set_fb(data->primary, fb);
igt_display_commit(display);
/* flip back the original white buffer */
igt_plane_set_fb(data->primary, &data->fb[0]);
igt_display_commit(display);
/* make sure caching mode has become UC/WT */
caching = gem_get_caching(data->drm_fd, fb->gem_handle);
igt_assert(caching == I915_CACHING_NONE || caching == I915_CACHING_DISPLAY);
/*
* firstly demonstrate the need for DMA_BUF_SYNC_START ("begin_cpu_access")
*/
if (ioctl_sync)
prime_sync_start(dma_buf_fd);
/* use dmabuf pointer to make the other fb all white too */
buf = malloc(fb->size);
igt_assert(buf != NULL);
memset(buf, 0xff, fb->size);
memcpy(ptr, buf, fb->size);
free(buf);
/* and flip to it */
igt_plane_set_fb(data->primary, fb);
igt_display_commit(display);
/* check that the crc is as expected, which requires that caches got flushed */
igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
igt_assert_crc_equal(&crc, &data->ref_crc);
/*
* now demonstrates the need for DMA_BUF_SYNC_END ("end_cpu_access")
*/
/* start over, writing non-white to the fb again and flip to it to make it
* fully flushed */
cr = igt_get_cairo_ctx(data->drm_fd, fb);
igt_paint_test_pattern(cr, fb->width, fb->height);
cairo_destroy(cr);
igt_plane_set_fb(data->primary, fb);
igt_display_commit(display);
/* sync start, to move to CPU domain */
if (ioctl_sync)
prime_sync_start(dma_buf_fd);
/* use dmabuf pointer in the same fb to make it all white */
buf = malloc(fb->size);
igt_assert(buf != NULL);
memset(buf, 0xff, fb->size);
memcpy(ptr, buf, fb->size);
free(buf);
/* if we don't change to the GTT domain again, the whites won't get flushed
* and therefore we demonstrates the need for sync end here */
if (ioctl_sync)
prime_sync_end(dma_buf_fd);
/* check that the crc is as expected, which requires that caches got flushed */
igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
igt_assert_crc_equal(&crc, &data->ref_crc);
}
