static void
imxccm_attach(device_t parent, device_t self, void *aux)
{
struct imxccm_softc * const sc = device_private(self);
struct axi_attach_args *aa = aux;
bus_space_tag_t iot = aa->aa_iot;
ccm_softc = sc;
sc->sc_dev = self;
sc->sc_iot = iot;
if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0, &sc->sc_ioh)) {
aprint_error(": can't map registers\n");
return;
}
for (u_int i=1; i <= IMX51_N_DPLLS; ++i) {
if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0,
&sc->sc_pll[i-1].pll_ioh)) {
aprint_error(": can't map pll registers\n");
return;
}
}
aprint_normal(": Clock control module\n");
aprint_naive("\n");
imx51_get_pll_freq(1);
imx51_get_pll_freq(2);
imx51_get_pll_freq(3);
aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n",
imx51_get_clock(IMX51CLK_ARM_ROOT),
imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
aprint_verbose_dev(self, "PLL1 clock=%d, PLL2 clock=%d, PLL3 clock=%d\n",
imx51_get_clock(IMX51CLK_PLL1),
imx51_get_clock(IMX51CLK_PLL2),
imx51_get_clock(IMX51CLK_PLL3));
aprint_verbose_dev(self,
"mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n",
imx51_get_clock(IMX51CLK_MAIN_BUS_CLK),
imx51_get_clock(IMX51CLK_AHB_CLK_ROOT),
imx51_get_clock(IMX51CLK_IPG_CLK_ROOT),
imx51_get_clock(IMX51CLK_PERCLK_ROOT));
aprint_verbose_dev(self, "ESDHC1 clock=%d\n",
imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT));
}
void
imxpwm_attach(struct imxpwm_softc *sc, void *aux)
{
struct axi_attach_args *aa = aux;
if (aa->aa_size == AXICF_SIZE_DEFAULT)
aa->aa_size = PWM_SIZE;
sc->sc_iot = aa->aa_iot;
sc->sc_intr = aa->aa_irq;
sc->sc_freq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
if (bus_space_map(aa->aa_iot, aa->aa_addr, aa->aa_size, 0, &sc->sc_ioh))
panic("%s: couldn't map", device_xname(sc->sc_dev));
imxpwm_attach_common(sc);
}
int
imxclock_get_timerfreq(struct imxclock_softc *sc)
{
unsigned int ipg_freq;
#if NIMXCCM > 0
ipg_freq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
#else
#ifndef IMX51_IPGCLK_FREQ
#error IMX51_IPGCLK_FREQ need to be defined.
#endif
ipg_freq = IMX51_IPGCLK_FREQ;
#endif
return ipg_freq;
}
static int
imx_gpt_attach(device_t dev)
{
struct imx_gpt_softc *sc;
int err;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->sc_dev = dev;
sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
sc->sc_iot = rman_get_bustag(sc->res[0]);
sc->sc_ioh = rman_get_bushandle(sc->res[0]);
switch (sc->sc_clksrc) {
case GPT_CR_CLKSRC_NONE:
device_printf(dev, "can't run timer without clock source\n");
return (EINVAL);
case GPT_CR_CLKSRC_EXT:
device_printf(dev, "Not implemented. Geve me the way to get "
"external clock source frequency\n");
return (EINVAL);
case GPT_CR_CLKSRC_32K:
sc->clkfreq = 32768;
break;
case GPT_CR_CLKSRC_IPG_HIGH:
sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2;
break;
default:
sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
}
device_printf(dev, "Run on %dKHz clock.\n", sc->clkfreq / 1000);
/* Reset */
WRITE4(sc, IMX_GPT_CR, GPT_CR_SWR);
/* Enable and setup counters */
WRITE4(sc, IMX_GPT_CR,
GPT_CR_CLKSRC_IPG | /* Use IPG clock */
GPT_CR_FRR | /* Just count (FreeRunner mode) */
GPT_CR_STOPEN | /* Run in STOP mode */
GPT_CR_WAITEN | /* Run in WAIT mode */
GPT_CR_DBGEN); /* Run in DEBUG mode */
/* Disable interrupts */
WRITE4(sc, IMX_GPT_IR, 0);
/* Tick every 10us */
/* XXX: must be calculated from clock source frequency */
WRITE4(sc, IMX_GPT_PR, 665);
/* Use 100 KHz */
sc->clkfreq = 100000;
/* Setup and enable the timer interrupt */
err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
NULL, sc, &sc->sc_ih);
if (err != 0) {
bus_release_resources(dev, imx_gpt_spec, sc->res);
device_printf(dev, "Unable to setup the clock irq handler, "
"err = %d\n", err);
return (ENXIO);
}
sc->et.et_name = "i.MXxxx GPT Eventtimer";
sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
sc->et.et_quality = 1000;
sc->et.et_frequency = sc->clkfreq;
sc->et.et_min_period = (MIN_PERIOD << 32) / sc->et.et_frequency;
sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = imx_gpt_timer_start;
sc->et.et_stop = imx_gpt_timer_stop;
sc->et.et_priv = sc;
et_register(&sc->et);
/* Disable interrupts */
WRITE4(sc, IMX_GPT_IR, 0);
/* ACK any panding interrupts */
WRITE4(sc, IMX_GPT_SR, (GPT_IR_ROV << 1) - 1);
if (device_get_unit(dev) == 0)
imx_gpt_sc = sc;
imx_gpt_timecounter.tc_frequency = sc->clkfreq;
tc_init(&imx_gpt_timecounter);
printf("clock: hz=%d stathz = %d\n", hz, stathz);
device_printf(sc->sc_dev, "timer clock frequency %d\n", sc->clkfreq);
imx_gpt_delay_count = imx51_get_clock(IMX51CLK_ARM_ROOT) / 4000000;
SET4(sc, IMX_GPT_CR, GPT_CR_EN);
return (0);
}
static int
imx_gpt_attach(device_t dev)
{
struct imx_gpt_softc *sc;
int ctlreg, err;
uint32_t basefreq, prescale;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->sc_dev = dev;
sc->sc_iot = rman_get_bustag(sc->res[0]);
sc->sc_ioh = rman_get_bushandle(sc->res[0]);
/*
* For now, just automatically choose a good clock for the hardware
* we're running on. Eventually we could allow selection from the fdt;
* the code in this driver will cope with any clock frequency.
*/
sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
ctlreg = 0;
switch (sc->sc_clksrc) {
case GPT_CR_CLKSRC_32K:
basefreq = 32768;
break;
case GPT_CR_CLKSRC_IPG:
basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
break;
case GPT_CR_CLKSRC_IPG_HIGH:
basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2;
break;
case GPT_CR_CLKSRC_24M:
ctlreg |= GPT_CR_24MEN;
basefreq = 24000000;
break;
case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */
case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */
default:
device_printf(dev, "Unsupported clock source '%d'\n",
sc->sc_clksrc);
return (EINVAL);
}
/*
* The following setup sequence is from the I.MX6 reference manual,
* "Selecting the clock source". First, disable the clock and
* interrupts. This also clears input and output mode bits and in
* general completes several of the early steps in the procedure.
*/
WRITE4(sc, IMX_GPT_CR, 0);
WRITE4(sc, IMX_GPT_IR, 0);
/* Choose the clock and the power-saving behaviors. */
ctlreg |=
sc->sc_clksrc | /* Use selected clock */
GPT_CR_FRR | /* Just count (FreeRunner mode) */
GPT_CR_STOPEN | /* Run in STOP mode */
GPT_CR_DOZEEN | /* Run in DOZE mode */
GPT_CR_WAITEN | /* Run in WAIT mode */
GPT_CR_DBGEN; /* Run in DEBUG mode */
WRITE4(sc, IMX_GPT_CR, ctlreg);
/*
* The datasheet says to do the software reset after choosing the clock
* source. It says nothing about needing to wait for the reset to
* complete, but the register description does document the fact that
* the reset isn't complete until the SWR bit reads 0, so let's be safe.
* The reset also clears all registers except for a few of the bits in
* CR, but we'll rewrite all the CR bits when we start the counter.
*/
WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR)
continue;
/* Set a prescaler value that gets us near the target frequency. */
if (basefreq < TARGET_FREQUENCY) {
prescale = 0;
sc->clkfreq = basefreq;
} else {
prescale = basefreq / TARGET_FREQUENCY;
sc->clkfreq = basefreq / prescale;
prescale -= 1; /* 1..n range is 0..n-1 in hardware. */
}
WRITE4(sc, IMX_GPT_PR, prescale);
/* Clear the status register. */
WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
/* Start the counter. */
WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN);
if (bootverbose)
device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n",
sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR));
/* Setup the timer interrupt. */
err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
NULL, sc, &sc->sc_ih);
if (err != 0) {
bus_release_resources(dev, imx_gpt_spec, sc->res);
device_printf(dev, "Unable to setup the clock irq handler, "
"err = %d\n", err);
return (ENXIO);
}
/* Register as an eventtimer. */
sc->et.et_name = "i.MXxxx GPT Eventtimer";
sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
sc->et.et_quality = 1000;
sc->et.et_frequency = sc->clkfreq;
sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency;
sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = imx_gpt_timer_start;
sc->et.et_stop = imx_gpt_timer_stop;
sc->et.et_priv = sc;
et_register(&sc->et);
/* Register as a timecounter. */
imx_gpt_timecounter.tc_frequency = sc->clkfreq;
tc_init(&imx_gpt_timecounter);
/* If this is the first unit, store the softc for use in DELAY. */
if (device_get_unit(dev) == 0)
imx_gpt_sc = sc;
return (0);
}
void
imx51_clk_rate(int clk_src, int clk_base, int rate)
{
#ifdef IMX50
bus_space_tag_t iot = ccm_softc->sc_iot;
bus_space_handle_t ioh = ccm_softc->sc_ioh;
uint32_t reg;
int div;
uint64_t freq = 0;
switch (clk_src) {
case CCGR_EPDC_AXI_CLK:
reg = bus_space_read_4(iot, ioh, CCMC_CLKSEQ_BYPASS);
reg &= ~CLKSEQ_EPDC_AXI_CLK;
reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_AXI_CLK);
bus_space_write_4(iot, ioh, CCMC_CLKSEQ_BYPASS, reg);
switch (clk_base) {
case CLKSEQ_XTAL:
freq = 24000000;
break;
case CLKSEQ_PFDx:
freq = imx51_get_clock(IMX50CLK_PFD3_CLK_ROOT);
break;
case CLKSEQ_PLL1:
freq = imx51_get_clock(IMX51CLK_PLL1);
break;
}
div = max(1, freq / rate);
reg = bus_space_read_4(iot, ioh, CCMC_EPDC_AXI);
reg &= ~EPDC_AXI_DIV;
reg |= __SHIFTIN(div, EPDC_AXI_DIV);
bus_space_write_4(iot, ioh, CCMC_EPDC_AXI, reg);
while (bus_space_read_4(iot, ioh, CCMC_CSR2) & CSR2_EPDC_AXI_BUSY)
; /* wait */
break;
case CCGR_EPDC_PIX_CLK:
reg = bus_space_read_4(iot, ioh, CCMC_CLKSEQ_BYPASS);
reg &= ~CLKSEQ_EPDC_PIX_CLK;
reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_PIX_CLK);
bus_space_write_4(iot, ioh, CCMC_CLKSEQ_BYPASS, reg);
switch (clk_base) {
case CLKSEQ_XTAL:
freq = 24000000;
break;
case CLKSEQ_PFDx:
freq = imx51_get_clock(IMX50CLK_PFD5_CLK_ROOT);
break;
case CLKSEQ_PLL1:
freq = imx51_get_clock(IMX51CLK_PLL1);
break;
case CLKSEQ_CAMP1:
/* XXX */
freq = 0;
break;
}
div = freq / rate;
reg = bus_space_read_4(iot, ioh, CCMC_EPDC_PIX);
reg &= ~EPDC_PIX_CLK_PRED;
reg |= __SHIFTIN(div, EPDC_PIX_CLK_PRED);
bus_space_write_4(iot, ioh, CCMC_EPDC_PIX, reg);
while (bus_space_read_4(iot, ioh, CCMC_CSR2) & CSR2_EPDC_PIX_BUSY)
; /* wait */
break;
}
#endif
}
u_int
imx51_get_clock(enum imx51_clock clk)
{
bus_space_tag_t iot = ccm_softc->sc_iot;
bus_space_handle_t ioh = ccm_softc->sc_ioh;
u_int freq = 0;
u_int sel;
uint32_t cacrr; /* ARM clock root register */
uint32_t ccsr;
uint32_t cscdr1;
uint32_t cscdr2;
uint32_t cscmr1;
uint32_t cbcdr;
uint32_t cbcmr;
uint32_t cdcr;
switch (clk) {
case IMX51CLK_PLL1:
case IMX51CLK_PLL2:
case IMX51CLK_PLL3:
return ccm_softc->sc_pll[clk - IMX51CLK_PLL1].pll_freq;
case IMX51CLK_PLL1SW:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
return ccm_softc->sc_pll[1-1].pll_freq;
/* step clock */
/* FALLTHROUGH */
case IMX51CLK_PLL1STEP:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL)) {
case 0:
return imx51_get_clock(IMX51CLK_LP_APM);
case 1:
return 0; /* XXX PLL bypass clock */
case 2:
return ccm_softc->sc_pll[2-1].pll_freq /
(1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF));
case 3:
return ccm_softc->sc_pll[3-1].pll_freq /
(1 + __SHIFTOUT(ccsr, CCSR_PLL3_DIV_PODF));
}
/*NOTREACHED*/
case IMX51CLK_PLL2SW:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0)
return imx51_get_clock(IMX51CLK_PLL2);
return 0; /* XXX PLL2 bypass clk */
case IMX51CLK_PLL3SW:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0)
return imx51_get_clock(IMX51CLK_PLL3);
return 0; /* XXX PLL3 bypass clk */
case IMX51CLK_LP_APM:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
return (ccsr & CCSR_LP_APM) ?
imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ;
case IMX51CLK_ARM_ROOT:
freq = imx51_get_clock(IMX51CLK_PLL1SW);
cacrr = bus_space_read_4(iot, ioh, CCMC_CACRR);
return freq / (cacrr + 1);
/* ... */
case IMX51CLK_MAIN_BUS_CLK_SRC:
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
#if IMX50
switch (__SHIFTOUT(cbcdr, CBCDR_PERIPH_CLK_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_PLL1SW);
break;
case 1:
freq = imx51_get_clock(IMX51CLK_PLL2SW);
break;
case 2:
freq = imx51_get_clock(IMX51CLK_PLL3SW);
break;
case 3:
freq = imx51_get_clock(IMX51CLK_LP_APM);
break;
}
#else
if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0)
freq = imx51_get_clock(IMX51CLK_PLL2SW);
else {
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_PLL1SW);
break;
case 1:
freq = imx51_get_clock(IMX51CLK_PLL3SW);
break;
case 2:
freq = imx51_get_clock(IMX51CLK_LP_APM);
break;
case 3:
/* XXX: error */
break;
}
}
#endif
return freq;
case IMX51CLK_MAIN_BUS_CLK:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR);
if (cdcr & CDCR_SW_PERIPH_CLK_DIV_REQ)
return freq / (1 + __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF));
else
return freq;
case IMX51CLK_AHB_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF));
case IMX51CLK_IPG_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF));
case IMX51CLK_PERCLK_ROOT:
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
if (cbcmr & CBCMR_PERCLK_IPG_SEL)
return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
if (cbcmr & CBCMR_PERCLK_LP_APM_SEL)
freq = imx51_get_clock(IMX51CLK_LP_APM);
else {
#ifdef IMX50
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
#else
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
#endif
}
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
#ifdef IMXCCMDEBUG
printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
#endif
freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED1);
freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED2);
freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PODF);
return freq;
case IMX51CLK_UART_CLK_ROOT:
cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
#ifdef IMXCCMDEBUG
printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
#endif
sel = __SHIFTOUT(cscmr1, CSCMR1_UART_CLK_SEL);
switch (sel) {
case 0:
case 1:
case 2:
freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
break;
case 3:
freq = imx51_get_clock(IMX51CLK_LP_APM);
break;
}
return freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PRED)) /
(1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF));
case IMX51CLK_IPU_HSP_CLK_ROOT:
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
break;
case 1:
freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK);
break;
case 2:
freq = imx51_get_clock(
IMX51CLK_EMI_SLOW_CLK_ROOT);
break;
case 3:
freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
break;
}
return freq;
#ifdef IMX50
case IMX51CLK_ESDHC2_CLK_ROOT:
case IMX51CLK_ESDHC4_CLK_ROOT:
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
sel = 0;
if (clk == IMX51CLK_ESDHC2_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC2_CLK_SEL);
else if (clk == IMX51CLK_ESDHC4_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC4_CLK_SEL);
if (sel == 0)
freq = imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT);
else
freq = imx51_get_clock(IMX51CLK_ESDHC3_CLK_ROOT);
return freq;
case IMX51CLK_ESDHC1_CLK_ROOT:
case IMX51CLK_ESDHC3_CLK_ROOT:
cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
sel = 0;
if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC1_CLK_SEL);
else if (clk == IMX51CLK_ESDHC3_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC3_CLK_SEL);
switch (sel) {
case 0:
case 1:
case 2:
freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
break;
case 3:
freq = imx51_get_clock(IMX51CLK_LP_APM);
break;
case 4:
/* PFD0 XXX */
break;
case 5:
/* PFD1 XXX */
break;
case 6:
/* PFD4 XXX */
break;
case 7:
/* osc_clk XXX */
break;
}
if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PRED)) /
(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PODF));
else if (clk == IMX51CLK_ESDHC3_CLK_ROOT)
freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PRED)) /
(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PODF));
return freq;
#else
case IMX51CLK_ESDHC3_CLK_ROOT:
case IMX51CLK_ESDHC4_CLK_ROOT:
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
sel = 0;
if (clk == IMX51CLK_ESDHC3_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC3_CLK_SEL);
else if (clk == IMX51CLK_ESDHC4_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC4_CLK_SEL);
if (sel == 0)
freq = imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT);
else
freq = imx51_get_clock(IMX51CLK_ESDHC2_CLK_ROOT);
return freq;
case IMX51CLK_ESDHC1_CLK_ROOT:
case IMX51CLK_ESDHC2_CLK_ROOT:
cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
sel = 0;
if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC1_CLK_SEL);
else if (clk == IMX51CLK_ESDHC2_CLK_ROOT)
sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC2_CLK_SEL);
switch (sel) {
case 0:
case 1:
case 2:
freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
break;
case 3:
freq = imx51_get_clock(IMX51CLK_LP_APM);
break;
}
if (clk == IMX51CLK_ESDHC1_CLK_ROOT)
freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PRED)) /
(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PODF));
else if (clk == IMX51CLK_ESDHC2_CLK_ROOT)
freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC2_CLK_PRED)) /
(1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC2_CLK_PODF));
return freq;
#endif
case IMX51CLK_CSPI_CLK_ROOT:
cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
cscdr2 = bus_space_read_4(iot, ioh, CCMC_CSCDR2);
sel = __SHIFTOUT(cscmr1, CSCMR1_CSPI_CLK_SEL);
switch (sel) {
case 0:
case 1:
case 2:
freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
break;
case 3:
freq = imx51_get_clock(IMX51CLK_LP_APM);
break;
}
freq = freq / (1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PRED)) /
(1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PODF));
return freq;
#if IMX50
case IMX50CLK_PFD0_CLK_ROOT:
case IMX50CLK_PFD1_CLK_ROOT:
case IMX50CLK_PFD2_CLK_ROOT:
case IMX50CLK_PFD3_CLK_ROOT:
case IMX50CLK_PFD4_CLK_ROOT:
case IMX50CLK_PFD5_CLK_ROOT:
case IMX50CLK_PFD6_CLK_ROOT:
case IMX50CLK_PFD7_CLK_ROOT:
freq = imx51_get_pfd_freq(clk - IMX50CLK_PFD0_CLK_ROOT);
return freq;
#endif
default:
aprint_error_dev(ccm_softc->sc_dev,
"clock %d: not supported yet\n", clk);
return 0;
}
}
