int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC2_BASE_ADDR:
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
ret = 1;
#else
imx_iomux_v3_setup_pad(usdhc2_cd_pad);
gpio_direction_input(USDHC2_CD_GPIO);
/*
* Since it is the DAT3 pin, this pin is pulled to
* low voltage if no card
*/
ret = gpio_get_value(USDHC2_CD_GPIO);
imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
#endif
break;
}
return ret;
}
static void setup_epdc(void)
{
/*** epdc Maxim PMIC settings ***/
/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set pixel clock rates for EPDC in clock.c */
panel_info.epdc_data.wv_modes.mode_init = 0;
panel_info.epdc_data.wv_modes.mode_du = 1;
panel_info.epdc_data.wv_modes.mode_gc4 = 3;
panel_info.epdc_data.wv_modes.mode_gc8 = 2;
panel_info.epdc_data.wv_modes.mode_gc16 = 2;
panel_info.epdc_data.wv_modes.mode_gc32 = 2;
panel_info.epdc_data.epdc_timings = panel_timings;
setup_epdc_power();
}
int board_ehci_hcd_init(int port)
{
/* Set USBH1_STP to GPIO and toggle it */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
MX51_USBH_PAD_CTRL));
gpio_direction_output(MX51EVK_USBH1_STP, 0);
gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
mdelay(10);
gpio_set_value(MX51EVK_USBH1_STP, 1);
/* Set back USBH1_STP to be function */
imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
/* De-assert USB PHY RESETB */
gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
/* Drive USB_CLK_EN_B line low */
gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
/* Reset USB hub */
gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
mdelay(2);
gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
return 0;
}
static void setup_epdc_power(void)
{
/* Setup epdc voltage */
/* EIM_A17 - GPIO2[21] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as input */
gpio_direction_input(IMX_GPIO_NR(2, 21));
/* EIM_D17 - GPIO3[17] for VCOM control */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(2, 20), 1);
}
static void setup_epdc_power(void)
{
/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
/* Setup epdc voltage */
/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(2, 31));
/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(2, 30), 1);
}
static void setup_epdc_power(void)
{
/* Setup epdc voltage */
/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(2, 13));
/* EPDC_VCOM0 - GPIO2[3] for VCOM control */
imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
/* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */
imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 |
MUX_PAD_CTRL(EPDC_PAD_CTRL));
/* Set as output */
gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
}
static int force_idle_bus(void *priv)
{
int i;
int sda, scl;
ulong elapsed, start_time;
struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
int ret = 0;
gpio_direction_input(p->sda.gp);
gpio_direction_input(p->scl.gp);
imx_iomux_v3_setup_pad(p->sda.gpio_mode);
imx_iomux_v3_setup_pad(p->scl.gpio_mode);
sda = gpio_get_value(p->sda.gp);
scl = gpio_get_value(p->scl.gp);
if ((sda & scl) == 1)
goto exit; /* Bus is idle already */
printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
sda, scl, p->sda.gp, p->scl.gp);
/* Send high and low on the SCL line */
for (i = 0; i < 9; i++) {
gpio_direction_output(p->scl.gp, 0);
udelay(50);
gpio_direction_input(p->scl.gp);
udelay(50);
}
start_time = get_timer(0);
for (;;) {
sda = gpio_get_value(p->sda.gp);
scl = gpio_get_value(p->scl.gp);
if ((sda & scl) == 1)
break;
WATCHDOG_RESET();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
ret = -EBUSY;
printf("%s: failed to clear bus, sda=%d scl=%d\n",
__func__, sda, scl);
break;
}
}
exit:
imx_iomux_v3_setup_pad(p->sda.i2c_mode);
imx_iomux_v3_setup_pad(p->scl.i2c_mode);
return ret;
}
int board_ehci_hcd_init(int port)
{
/* request VBUS power enable pin, GPIO7_8 */
imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
return 0;
}
static void m53_set_clock(void)
{
int ret;
const uint32_t ref_clk = MXC_HCLK;
const uint32_t dramclk = 400;
uint32_t cpuclk;
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
gpio_direction_input(IMX_GPIO_NR(4, 0));
/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
if (ret)
printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
if (ret) {
printf("CPU: Switch peripheral clock to %dMHz failed\n",
dramclk);
}
ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
if (ret)
printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
}
int board_mmc_getcd(struct mmc *mmc)
{
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
gpio_direction_input(IMX_GPIO_NR(1, 1));
return !gpio_get_value(IMX_GPIO_NR(1, 1));
}