void pci_target_init(struct pci_controller * hose ) { /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ out32r( PCIX0_PIM0SA, 0 ); /* disable */ out32r( PCIX0_PIM1SA, 0 ); /* disable */ out32r( PCIX0_PIM2SA, 0 ); /* disable */ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ /*-------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); out32r( PCIX0_BAR0, 0 ); /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); }
void show_xbridge_info(void) { unsigned long reg; printf("PCI-X chip control registers\n"); mfsdr(sdr_xcr, reg); printf("sdr_xcr = %#010x\n", reg); mfsdr(sdr_xpllc, reg); printf("sdr_xpllc = %#010x\n", reg); mfsdr(sdr_xplld, reg); printf("sdr_xplld = %#010x\n", reg); printf("PCI-X Bridge Configure registers\n"); printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID)); printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID)); printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD)); printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS)); printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID)); printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS)); printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM)); printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE)); printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST)); printf("PCIX0_BAR0 = %#010x\n", in32r(PCIX0_BAR0)); printf("PCIX0_BAR1 = %#010x\n", in32r(PCIX0_BAR1)); printf("PCIX0_BAR2 = %#010x\n", in32r(PCIX0_BAR2)); printf("PCIX0_BAR3 = %#010x\n", in32r(PCIX0_BAR3)); printf("PCIX0_BAR4 = %#010x\n", in32r(PCIX0_BAR4)); printf("PCIX0_BAR5 = %#010x\n", in32r(PCIX0_BAR5)); printf("PCIX0_CISPTR = %#010x\n", in32r(PCIX0_CISPTR)); printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID)); printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID)); printf("PCIX0_EROMBA = %#010x\n", in32r(PCIX0_EROMBA)); printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP)); printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN)); printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN)); printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT)); printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY)); printf("PCIX0_BRDGOPT1 = %#010x\n", in32r(PCIX0_BRDGOPT1)); printf("PCIX0_BRDGOPT2 = %#010x\n", in32r(PCIX0_BRDGOPT2)); printf("PCIX0_POM0LAL = %#010x\n", in32r(PCIX0_POM0LAL)); printf("PCIX0_POM0LAH = %#010x\n", in32r(PCIX0_POM0LAH)); printf("PCIX0_POM0SA = %#010x\n", in32r(PCIX0_POM0SA)); printf("PCIX0_POM0PCILAL = %#010x\n", in32r(PCIX0_POM0PCIAL)); printf("PCIX0_POM0PCILAH = %#010x\n", in32r(PCIX0_POM0PCIAH)); printf("PCIX0_POM1LAL = %#010x\n", in32r(PCIX0_POM1LAL)); printf("PCIX0_POM1LAH = %#010x\n", in32r(PCIX0_POM1LAH)); printf("PCIX0_POM1SA = %#010x\n", in32r(PCIX0_POM1SA)); printf("PCIX0_POM1PCILAL = %#010x\n", in32r(PCIX0_POM1PCIAL)); printf("PCIX0_POM1PCILAH = %#010x\n", in32r(PCIX0_POM1PCIAH)); printf("PCIX0_POM2SA = %#010x\n", in32r(PCIX0_POM2SA)); printf("PCIX0_PIM0SA = %#010x\n", in32r(PCIX0_PIM0SA)); printf("PCIX0_PIM0LAL = %#010x\n", in32r(PCIX0_PIM0LAL)); printf("PCIX0_PIM0LAH = %#010x\n", in32r(PCIX0_PIM0LAH)); printf("PCIX0_PIM1SA = %#010x\n", in32r(PCIX0_PIM1SA)); printf("PCIX0_PIM1LAL = %#010x\n", in32r(PCIX0_PIM1LAL)); printf("PCIX0_PIM1LAH = %#010x\n", in32r(PCIX0_PIM1LAH)); printf("PCIX0_PIM2SA = %#010x\n", in32r(PCIX0_PIM1SA)); printf("PCIX0_PIM2LAL = %#010x\n", in32r(PCIX0_PIM1LAL)); printf("PCIX0_PIM2LAH = %#010x\n", in32r(PCIX0_PIM1LAH)); printf("PCIX0_XSTS = %#010x\n", in32r(PCIX0_STS)); }
int pci_440_init (struct pci_controller *hose) { int reg_num = 0; #ifndef CONFIG_DISABLE_PISE_TEST /*--------------------------------------------------------------------------+ * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; mfsdr(sdr_sdstp1,strap); if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); return -1; } #elif defined(CONFIG_440GP) unsigned long strap; strap = mfdcr(cpc0_strp1); if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); return -1; } #endif #endif /* CONFIG_DISABLE_PISE_TEST */ /*--------------------------------------------------------------------------+ * PCI controller init *--------------------------------------------------------------------------*/ hose->first_busno = 0; hose->last_busno = 0; /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, 0x00000000, PCIX0_IOBASE, 0x10000, PCI_REGION_IO); /* PCI memory space */ pci_set_region(hose->regions + reg_num++, CONFIG_SYS_PCI_TARGBASE, CONFIG_SYS_PCI_MEMBASE, #ifdef CONFIG_SYS_PCI_MEMSIZE CONFIG_SYS_PCI_MEMSIZE, #else 0x10000000, #endif PCI_REGION_MEM ); #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ defined(CONFIG_PCI_SYS_MEM_SIZE) /* System memory space */ pci_set_region(hose->regions + reg_num++, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, CONFIG_PCI_SYS_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY ); #endif hose->region_count = reg_num; pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); /* Let board change/modify hose & do initial checks */ if (pci_pre_init (hose) == 0) { printf("PCI: Board-specific initialization failed.\n"); printf("PCI: Configuration aborted.\n"); return -1; } pci_register_hose( hose ); /*--------------------------------------------------------------------------+ * PCI target init *--------------------------------------------------------------------------*/ #if defined(CONFIG_SYS_PCI_TARGET_INIT) pci_target_init(hose); /* Let board setup pci target */ #else out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ #endif /*--------------------------------------------------------------------------+ * PCI master init: default is one 256MB region for PCI memory: * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE *--------------------------------------------------------------------------*/ #if defined(CONFIG_SYS_PCI_MASTER_INIT) pci_master_init(hose); /* Let board setup pci master */ #else out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_POM0LAL, 0x10000000 ); out32r( PCIX0_POM0LAH, 0x0000000c ); #else out32r( PCIX0_POM0LAL, 0x00000000 ); out32r( PCIX0_POM0LAH, 0x00000003 ); #endif out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); out32r( PCIX0_POM0PCIAH, 0x00000000 ); out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); #endif /*--------------------------------------------------------------------------+ * PCI host configuration -- we don't make any assumptions here ... the * _board_must_indicate_ what to do -- there's just too many runtime * scenarios in environments like cPCI, PPMC, etc. to make a determination * based on hard-coded values or state of arbiter enable. *--------------------------------------------------------------------------*/ if (is_pci_host(hose)) { #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); #endif hose->last_busno = pci_hose_scan(hose); } return hose->last_busno; }