BOOL DR_VendorCmnd(void)
{
WORD value;
WORD len,ind, bc; // xdata used here to conserve data ram; if not EEPROM writes don't work anymore
/*
union {
unsigned short ushort;
unsigned msb,lsb;
unsigned bytes[2]; // big endian, bytes[0] is MSB as far as C51 is concerned
} length;
*/
WORD i;
char *dscrRAM;
unsigned char xdata JTAGdata[400];
switch (SETUPDAT[1]){
case VR_ENABLE_AE_IN: // enable IN transfers
{
startMonitor();
break; // handshake phase triggered below
}
case VR_DISABLE_AE_IN: // disable IN transfers
{
stopMonitor();
break;
}
case VR_RESET_FIFOS: // reset in and out fifo
{
SYNCDELAY;
EP6FIFOCFG = 0x00; //0000_0000 disable auto-in
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x08 ; //0000_1000 reenable auto-in
break;
}
case VR_DOWNLOAD_CPLD_CODE:
{
if (SETUPDAT[0]==VR_DOWNLOAD) {
if (JTAGinit)
{
IOC=0x00;
OEC = 0xBD; // configure TDO (bit 6) and TSmaster as input : 1011_1101
xsvfInitialize();
JTAGinit=FALSE;
}
len = SETUPDAT[6];
len |= SETUPDAT[7] << 8;
if (len>400)
{
xsvfReturn=10;
OEC = 0x0D; // configure JTAG pins to float : 0000_1111
JTAGinit=TRUE;
break;
}
value=0;
resetReadCounter(JTAGdata);
while(len) // Move new data through EP0OUT
{ // one packet at a time.
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
while(EP0CS & bmEPBUSY);
bc = EP0BCL; // Get the new bytecount
for(i=0; i<bc; i++)
JTAGdata[value+i] = EP0BUF[i];
value += bc;
len -= bc;
}
if (SETUPDAT[2]==0x00) //complete
{
OEC = 0x0D; // configure JTAG pins to float : 0000_1111
JTAGinit=TRUE;
} else
{
xsvfReturn=xsvfRun();
if (xsvfReturn>0) // returns true if error
{
OEC = 0x0D; // configure JTAG pins to float : 0000_1101
JTAGinit=TRUE;
// return TRUE;
}
}
/* EP0BUF[0] = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
return(FALSE); */
break;
}
else //case VR_XSVF_ERROR_CODE:
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= xsvfReturn;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
return(FALSE);
}
}
case VR_SET_DEVICE_NAME:
{
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
while(EP0CS & bmEPBUSY); //wait for the data packet to arrive
dscrRAM = (char*)EZUSB_GetStringDscr(3); // get address of serial number descriptor-string in RAM
if (EP0BCL > MAX_NAME_LENGTH)
{
len=MAX_NAME_LENGTH;
} else
{
len=EP0BCL;
}
for (i=0;i<len;i++)
{
EEPROMWriteBYTE(STRING_ADDRESS+i, EP0BUF[i]); // write string to EEPROM
dscrRAM[2+i*2] = EP0BUF[i]; // write string to RAM
}
for (i=len; i<MAX_NAME_LENGTH; i++) // fill the rest with stop characters
{
EEPROMWriteBYTE(STRING_ADDRESS+i, ' '); // write string to EEPROM
dscrRAM[2+i*2] = ' '; // write string to RAM
}
EP0BCH = 0;
EP0BCL = 0;
return(FALSE);
}
case VR_RESETTIMESTAMPS:
{
tsReset=1; // RESET_TS=1; // assert RESET_TS pin for one instruction cycle (four clock cycles)
tsReset=0; // RESET_TS=0;
break;
}
case VR_CONFIG: // write bytes to SPI interface
case VR_EEPROM_BIASGEN_BYTES: // falls through and actual command is tested below
{
// the value bytes are the specific config command
// the index bytes are the arguments
// more data comes in the setupdat
SYNCDELAY;
value = SETUPDAT[2]; // Get request value
value |= SETUPDAT[3] << 8; // data comes little endian
ind = SETUPDAT[4]; // Get index
ind |= SETUPDAT[5] << 8;
len = SETUPDAT[6]; // length for data phase
len |= SETUPDAT[7] << 8;
switch(value&0xFF){ // take LSB for specific setup command because equalizer uses MSB for channel
// final short CMD_IPOT = 1, CMD_RESET_EQUALIZER = 2, CMD_SCANNER = 3, CMD_EQUALIZER = 4, CMD_SETBIT = 5, CMD_VDAC = 6;
#define CMD_IPOT 1
#define CMD_RESET_EQUALIZER 2
#define CMD_SCANNER 3
#define CMD_EQUALIZER 4
#define CMD_SETBIT 5
#define CMD_VDAC 6
#define CMD_INITDAC 7
case CMD_IPOT:
selectIPots;
numBiasBytes=len;
while(len){ // Move new data through EP0OUT, one packet at a time,
// eventually will get len down to zero by bc=64,64,15 (for example)
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
bc = EP0BCL; // Get the new bytecount
for(i=0; i<bc; i++){
sendConfigByte(EP0BUF[i]);
}
// value += bc; // inc eeprom value to write to, in case that's what we're doing
len -= bc; // dec total byte count
}
toggleLatch();
selectNone;
LED=!LED;
break;
case CMD_VDAC:
// EP0BUF has b0=channel (same for each DAC), b1=DAC1 MSB, b2=DAC1 LSB, b3=DAC0 MSB, b4=DAC0 LSB
if(len!=6) return TRUE; // error, should have 6 bytes which are just written out to DACs surrounded by dacNSync=0
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
startDACSync();
for(i=0;i<6;i++){
sendDACByte(EP0BUF[i]);
}
endDACSync();
//toggleLDAC();
LED=!LED;
break;
case CMD_INITDAC:
initDAC();
LED=!LED;
break;
case CMD_SETBIT:
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
// sends value=CMD_SETBIT, index=portbit with (port(b=0,d=1,e=2)<<8)|bitmask(e.g. 00001000) in MSB/LSB, byte[0]=value (1,0)
// also if button is tristable type in GUI, then byte[0] has tristate in bit1
{
bit bitval=(EP0BUF[0]&1); // 1=set, 0=clear
bit tristate=(EP0BUF[0]&2?1:0); // 1=tristate, 0=drive
unsigned char bitmask=SETUPDAT[4]; // bitmaskit mask, LSB of ind
switch(SETUPDAT[5]){ // this is port, MSB of ind
case 0: // port c
if(bitval) IOC|=bitmask; else IOC&= ~bitmask;
if(tristate) OEC&= ~bitmask; else OEC|=bitmask;
break;
case 1: // port d
if(bitval) IOD|=bitmask; else IOD&= ~bitmask;
if(tristate) OED&= ~bitmask; else OED|=bitmask;
break;
case 2: // port e
if(bitval) IOE|=bitmask; else IOE&= ~bitmask;
if(tristate) OEE&= ~bitmask; else OEE|=bitmask;
break;
default:
return TRUE; // error
}
LED=!LED;
}
break;
case CMD_SCANNER:
// index=1, continuous, index=0 go to channel
// Arm endpoint - do it here to clear (after sud avail) and get the data for channel to scan to if there is one. in any case must read data
// or subsequent requests will fail.
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
if(ind==0){ // go to channel
ET2=0; // disable timer2 interrupt - IE.5
TR2=0; // stop timer2
i=255; // timeout on scanner clear
while(IOE&ScanSync && i-->0){ // clock scanner to end and timeout if there is no chip there
scanClock=1; // sync happens on falling edge
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
scanClock=0;
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
}
if(i==0) return TRUE; // scan to start failed
bc = EP0BUF[0]; // Get the channel number to scan to
for(i=0; i<bc; i++){
scanClock=1; _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
scanClock=0; _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
}
}else{ // continuous scanning
RCAP2L=0xff-EP0BUF[0]; // load timer 2 low byte reload register with 0xff-period. period=0 reload is 0xff00 (255 counts), period=255, reload is 0x0000, period=64k
ET2=1; // enable timer2 interrupt - this is IE.5 bit addressable
TR2=1; // run timer2
}
LED=!LED;
break;
case CMD_EQUALIZER:
/*
the scheme right now for loading the AERKillBit and the local Vq's go as follows,
start with AddSel, which has 7 bits, RX0 to RX6, toggle bitlatch low/high - this signal
latches the bits for the decoder.
The output of the decoder is not activated till DataSel is chosen, the 10 bits are loaded, 5 bits
for Vq of SOS and 5bits for Iq of bpf, then when bitlatch is toggled low/high, then the
output of the decoder is released.
During this toggle of latch, the selected channel will also latch in the value on AERKillBit.
The only thing that I'm worrying about right now is that this value has to be remembered somewhere,
i.e. if I choose channels 10, 15 neurons to be inactivated, then even if I choose
new values for Vq and Iq, this information has to be stored somewhere. The
AERKillBit in essence is like an additional bit to the bits for the DataSel.
*/
// value has cmd in LSB, channel in MSB
// index has b11=bpfkilled, b10=lpfkilled, b9-5=qbpf, b4-0=qsos
/*All other 16-bit and 32-bit values are stored, contrary to other Intel
processors, in big endian format, with the high-order byte stored first. For
example, the LJMP and LCALL instructions expect 16-bit addresses that are
in big endian format.
*/
// index is channel address, bytes={gain,quality,killed (1=killed,0=active)}
selectAddr;
sendConfigBits(SETUPDAT[3],7); // send 7 bit address
toggleLatch();
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
selectNone;
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
selectData;
sendConfigBits(SETUPDAT[4]&0x1f,5); // what is this for?
sendConfigBits((SETUPDAT[4]>>5)|(SETUPDAT[5]<<3),5);
/* commented out because of bug in cochleaams1b where select of a single kill bit is inverted so everybody but the one you want
is selected. however, the equalizer DAC current splitters still work
// set each killbit
selectLPFKill; // clears ybit
if(SETUPDAT[5]&4){ // kill LPF
aerKillBit=0; // hack
}else{
aerKillBit=0;
}
toggleLatch();
selectBPFKill; // sets ybit
if(SETUPDAT[5]&8){ // kill BPF
aerKillBit=0; // hack
}else{
aerKillBit=0;
}
*/
toggleLatch();
selectNone;
LED=!LED;
break;
case CMD_RESET_EQUALIZER:
return TRUE; // not yet implmented
LED=!LED;
break;
default:
return(TRUE); // don't recognize command
}
EP0BCH = 0;
EP0BCL = 0; // Arm endpoint with 0 byte to transfer
return(FALSE); // very important, otherwise get stall
}
case VR_SET_POWERDOWN: // control powerDown output bit
{
if (SETUPDAT[2])
{
powerDown=1;
} else
{
powerDown=0;
}
*EP0BUF=VR_SET_POWERDOWN;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
SYNCDELAY;
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break; // very important, otherwise get stall
}
/*
case VR_SETARRAYRESET: // set array reset, based on lsb of argument
{
if (SETUPDAT[2]&0x01)
{
IOE=IOE|ARRAY_RESET_MASK; //IOE|=arrayReset;
} else
{
IOE=IOE&NOT_ARRAY_RESET_MASK;
}
*EP0BUF=VR_SETARRAYRESET;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return(FALSE); // very important, otherwise get stall
}
case VR_DOARRAYRESET: // reset array for fixed reset time
{
IOE=IOE&NOT_ARRAY_RESET_MASK;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_(); // a few us
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
IOE=IOE|ARRAY_RESET_MASK; //IOE|=arrayReset;
*EP0BUF=VR_DOARRAYRESET;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return (FALSE); // very important, otherwise get stall
}
*/
/* case VR_TIMESTAMP_TICK:
{
if (SETUPDAT[0]==VR_UPLOAD) //1010_0000 :vendor request to device, direction IN
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= operationMode;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
} else
{
operationMode=SETUPDAT[2];
if (operationMode==0)
{
TIMESTAMP_MODE = 0;
CFG_TIMESTAMP_COUNTER = 0;
}else if (operationMode==1)
{
CFG_TIMESTAMP_COUNTER = 1;
TIMESTAMP_MODE = 0;
}else if (operationMode==2)
{
CFG_TIMESTAMP_COUNTER = 0;
TIMESTAMP_MODE = 1;
}else if (operationMode==3)
{
CFG_TIMESTAMP_COUNTER = 1;
TIMESTAMP_MODE = 1;
}
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
}
return(FALSE);
}*/
case VR_IS_TS_MASTER:
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= TIMESTAMP_MASTER;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
return(FALSE);
}
/* case VR_MISSED_EVENTS:
{
EX1=0;
EP0BUF[0] = SETUPDAT[1];
EP0BUF[4]= (missedEvents & 0xFF000000) >> 24;
EP0BUF[3]= (missedEvents & 0x00FF0000) >> 16;
EP0BUF[2]= (missedEvents & 0x0000FF00) >> 8;
EP0BUF[1]= missedEvents & 0x000000FF;
EP0BCH = 0;
EP0BCL = 5;
EP0CS |= bmHSNAK;
missedEvents=0;
EX1=1;
return(FALSE);
}*/
case VR_RAM:
case VR_EEPROM:
{
value = SETUPDAT[2]; // Get address and length
value |= SETUPDAT[3] << 8;
len = SETUPDAT[6];
len |= SETUPDAT[7] << 8;
// Is this an upload command ?
if(SETUPDAT[0] == VR_UPLOAD) // this is automatically defined on host from direction of vendor request
{
while(len) // Move requested data through EP0IN
{ // one packet at a time.
while(EP0CS & bmEPBUSY);
if(len < EP0BUFF_SIZE)
bc = len;
else
bc = EP0BUFF_SIZE;
// Is this a RAM upload ?
if(SETUPDAT[1] == VR_RAM)
{
for(i=0; i<bc; i++)
*(EP0BUF+i) = *((BYTE xdata *)value+i);
}
else
{
for(i=0; i<bc; i++)
*(EP0BUF+i) = 0xcd;
EEPROMRead(value,(WORD)bc,(WORD)EP0BUF);
}
EP0BCH = 0;
EP0BCL = (BYTE)bc; // Arm endpoint with # bytes to transfer
value += bc;
len -= bc;
}
}
// Is this a download command ?
else if(SETUPDAT[0] == VR_DOWNLOAD) // this is automatically defined on host from direction of vendor request
{
while(len) // Move new data through EP0OUT
{ // one packet at a time.
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
while(EP0CS & bmEPBUSY);
bc = EP0BCL; // Get the new bytecount
// Is this a RAM download ?
if(SETUPDAT[1] == VR_RAM)
{
for(i=0; i<bc; i++)
*((BYTE xdata *)value+i) = *(EP0BUF+i);
}
else
EEPROMWrite(value,bc,(WORD)EP0BUF);
value += bc;
len -= bc;
}
}
return(FALSE);
}
default:
{ // we received an invalid command
return(TRUE);
}
}
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
return(FALSE);
}
void main(void)
{
unsigned int i,sweep=0;
DAC_DATA data;
byte test;
BYTE bdata;
deassertCSB0();
deassertCSB1();
deassertCSB2();
deassertCSB3();
deassertCSB4();
deassertCSB5();
deassertCSB6();
openFulldSPI();
openHalfdSPI();
//initTERM();
initCAN();
initDAC(0);
resetCLKD();
resetADC();
//Configuring AD9510 PLL Loop.
//In Fixed Divider mode (for N feedback divider), we have:
//Fvco = Fref * N/R
//Thus, N/R = 2 for Fvco = 125 MHz and Fref = 62.5 MHz.
//Where N is the feedback divider and R is the reference divider.
//Let N = 2 and R = 1. See below.
//R divider (Reference divider)
//R divider is set to '1'.
writeCLKD(0x0C, 0x01);
writeCLKD(0x0B, 0x00);
//N divider (Vco feedback divider)
//N divider: N(P, A, B).
//N = P*B+A.
//P is a prescaler (3 bits).
//A and B are counters, 6 and 3 bits respectively.
//Two modes are possible: FD (fixedd divider) and DM (dual modulus).
//In FD mode, A is not used.
//Set P prescaler to 2 and set B counter to 1 (bypass). Also set PLL to Normal Operation.
writeCLKD(0x0A, 0x44);
writeCLKD(0x07, 0x04); //Enable Loss of Reference (LOR) function.
writeCLKD(0x08, 0x0F); //Set Normal Operation mode to CP and STATUS Pin to 'Loss of Lock (active high)'.
//writeCLKD(0x08, 0x0D); //Set Pump-up mode to CP and STATUS Pin to 'Loss of Lock (active high)'.
//writeCLKD(0x08, 0x37); //Set Normal Operation mode to CP and STATUS Pin to 'Loss of Lock or Loss of Ref (active high)'.
//writeCLKD(0x08, 0x2B); //Set Normal Operation to CP and STATUS Pin to 'Loss of Ref (active high)'.
//writeCLKD(0x08, 0x35); //Set Pump-up mode to CP and STATUS Pin to 'Loss of Lock or Loss of Ref (active high)'.
//writeCLKD(0x09, 0x40); //Set CP current to 3.0 mA.
writeCLKD(0x09, 0x00); //Set CP current to 0.6 mA.
writeCLKD(0x45, 0x02); //Set CLK2 as Distribution input, power down CLK1 input. See doc.
writeCLKD(0x42, 0x02); //Enable OUT6
writeCLKD(0x43, 0x02); //Enable OUT7
writeCLKD(0x4B, 0xC0); //(OUT1) Set 'Ignore Chip-Level Sync Signal' and 'Bypass and Power-Down Divider Logic'. See doc.
writeCLKD(0x51, 0xC0); //(OUT4 - ADC78) Set 'Ignore Chip-Level Sync Signal' and 'Bypass and Power-Down Divider Logic'. See doc.
writeCLKD(0x53, 0xC0); //(OUT5 - ADC56) Set 'Ignore Chip-Level Sync Signal' and 'Bypass and Power-Down Divider Logic'. See doc.
writeCLKD(0x55, 0xC0); //(OUT6 - ADC34) Set 'Ignore Chip-Level Sync Signal' and 'Bypass and Power-Down Divider Logic'. See doc.
writeCLKD(0x57, 0xC0); //(OUT7 - ADC12) Set 'Ignore Chip-Level Sync Signal' and 'Bypass and Power-Down Divider Logic'. See doc.
//writeCLKD(0x57, 0x40); //(OUT7 - ADC12) Divider Logic Enabled - Dividing by 2 (Default) - Phase 0.
//writeCLKD(0x55, 0x41); //(OUT6 - ADC34) Divider Logic Enabled - Dividing by 2 (Default) - Phase 1.
//test = readCLKD(0x45);
writeCLKD(0x5A, 0x01); //Update Registers with SPI Buffers Content.
/*********************************/
//for ADC12
writeADC(1, 0x08, 0x00); //0x00: Normal op. - 0x01: Full Power Down.
writeADC(1, 0x14, 0xC1); //LVDS and two's comlement.
writeADC(1, 0x0D, 0x00); //Self Test - 0x00: Normal op. - 0x07: one/zero word toggle.
writeADC(1, 0xFF, 0x01); //Master Register latch enable - self resetable.
//for ADC34
writeADC(2, 0x08, 0x00);
writeADC(2, 0x14, 0xC1);
writeADC(2, 0xFF, 0x01);
//for ADC56
writeADC(4, 0x08, 0x00);
writeADC(4, 0x14, 0xC1);
writeADC(4, 0xFF, 0x01);
//for ADC78
writeADC(3, 0x08, 0x00); //0x01
writeADC(3, 0x14, 0xC1);
writeADC(3, 0xFF, 0x01);
data.wdata = 512; //~313mV
writeDAC(5, 0, data);
writeDAC(5, 1, data);
writeDAC(5, 2, data);
writeDAC(5, 3, data);
writeDAC(5, 4, data);
writeDAC(5, 5, data);
writeDAC(5, 6, data);
writeDAC(5, 7, data);
for(;;)
{
//test = readCLKD(0x45);
//writeCLKD(0x5A, 0x01);
//bdata._byte = 0xAA;
//writeHSPI(bdata);
for(i=0;i<10000;i++);
//data.wdata = sweep;
//writeDAC(5, 0, data);
//writeDAC(6, 0, data);
//sweep++;
//if (sweep>4095) sweep = 0;
//rxCAN();
}
//for(;;);
}
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
//CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
CPUCS = 0x12 ; // 1_0010 : CLKSP1:0=10, cpu clockspeed 48MHz, drive CLKOUT output pin 100 which clocks CPLD
/*
(from raphael berner: the clocking is as follows:
the fx2 clockes the CPLD by the CLKOUT pin (pin 100), and the CPLD clocks
the fifointerface on IFCLK, so in the firmware you should select external
clocksource in the FX2 for the slave FIFO clock source.
*/
IOC = 0x00;
IOA = 0x00;
IOE= 0x00; // set port output default values - enable them as outputs next
OEA = 0x8b; // 1000_1011. PA7 LED, PA3: nResetCPLD, PA1: runCPLD, PA0: tsReset
// port B is used as FD7-0 for 8 bit FIFO interface to CPLD
OEC = 0x0F; // now are cochlea and offchip DAC controls, before was 0000_1101 // JTAG, timestampMode, timestampTick, timestampMaster, resetTimestamp
OED = 0xFF; // all bit addressable outputs, all WORDWIDE=0 so port d should be enabled
OEE = 0x7F; // all outputs except scansync which is input, byte addressable
// set the slave FIFO interface to 30MHz, slave fifo mode
// select slave FIFO mode with with FIFO clock source as external clock (from CPLD).
// if the CPLD is not programmed there will not be any FIFO clock!
// if there is no IFCLK then the port D pins are never enabled as outputs.
// start with internal clock, switch to external CPLD clock source at end of TD_Init
SYNCDELAY;
IFCONFIG = 0xA3; // 0000_0011 // external clock, 30MHz, don't drive clock IFCLKOE, slave FIFO mode
SYNCDELAY; // may not be needed
// disable interrupts by the input pins and by timers and serial ports. timer2 scanner interrupt enabled when needed from vendor request.
IE &= 0x00; // 0000_0000
// disable interrupt pins 4, 5 and 6
EIE &= 0xE3; // 1110_0011;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
//disable all ports A,C,E alternate functions
SYNCDELAY;
PORTCCFG = 0x00;
SYNCDELAY;
PORTACFG = 0x00; // do not use interrupts 0 and 1
SYNCDELAY;
PORTECFG = 0x00;
EP1OUTCFG = 0x00; // EP1OUT disabled
SYNCDELAY;
EP1INCFG = 0xA0; // 1010 0000 VALID+Bulk EP1IN enabled, bulk
SYNCDELAY;
EP2CFG = 0x00; // EP2 disabled
SYNCDELAY;
EP4CFG = 0x00; // EP4 disabled
SYNCDELAY;
EP6CFG = 0xE0; // EP6 enabled, in bulk, quad buffered
SYNCDELAY;
EP8CFG = 0x00; // EP8 disabled
SYNCDELAY;
REVCTL= 0x03;
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP6AUTOINLENH=0x02;
SYNCDELAY;
EP6AUTOINLENL=0x00;
SYNCDELAY;
EP6FIFOCFG = 0x08 ; //0000_1000, autoin=1, wordwide=0 to automatically commit packets and make this an 8 bit interface to FD
SYNCDELAY;
EP2FIFOCFG = 0x00 ; // wordwide=0
SYNCDELAY;
EP4FIFOCFG = 0x00 ;
SYNCDELAY;
EP8FIFOCFG = 0x00 ;
//set FIFO flag configuration: FlagB: EP6 full, flagC and D unused
SYNCDELAY;
PINFLAGSAB = 0xE8; // 1110_1000
SYNCDELAY;
cycleCounter=0;
// missedEvents=0xFFFFFFFF; // one interrupt is generated at startup, maybe some cpld registers start in high state
LED=1; // turn on LED
clock=1; bitIn=0; latch=0; powerDown=0; // init biasgen ports and pins
EZUSB_InitI2C(); // init I2C to enable EEPROM read and write
JTAGinit=TRUE;
IT0=1; // make INT0# edge-sensitive
EX0=0; // do not enable INT0#
IT1=1; // INT1# edge-sensitve
EX1=0; // do not enable INT1#
// timer2 init for scanner clocking in continuous mode
T2CON=0x00; // 0000 0100 timer2 control, set to 16 bit with autoreload, timer stopped
RCAP2L=0x00; // timer 2 low register loaded from vendor request.
RCAP2H=0xFF; // starting reload values, counter counts up to 0xFFFF from these and generates interrupt when count rolls to 0
ET2=0; // disable interrupt to start
/* // not using now writing initial bias values
for (i=0;i<NUM_BIAS_BYTES;i++)
{
spiwritebyte(biasBytes[i]);
}
latchNewBiases();
*/
toggleVReset();
// now switch to external IFCLK for FIFOs
// SYNCDELAY; // may not be needed
// IFCONFIG = 0x23; // 0010_0011 // extenal clock, slave fifo mode
// SYNCDELAY; // may not be needed
initDAC();
}
