int board_late_init(void) { init_ethernet_mac(); init_pcie_bridge(); init_pcie(); finish_spiboot(); return 0; }
/******************************************************************************* * Function which will perform any remaining platform-specific setup that can * occur after the MMU and data cache have been enabled. ******************************************************************************/ void bl1_platform_setup(void) { init_nic400(); init_pcie(); /* Initialise the IO layer and register platform IO devices */ io_setup(); /* Enable and initialize the System level generic timer */ mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); }
void gm45_late_init(const stepping_t stepping) { const device_t mch = PCI_DEV(0, 0, 0); const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1; const int peg_x16 = (peg_enabled && !sdvo_enabled); init_egress(); init_dmi(stepping >= STEPPING_B2); init_pcie(peg_enabled, sdvo_enabled, peg_x16); setup_aspm(stepping, peg_enabled); setup_rcrb(peg_enabled); }