static void __init ruffian_init_irq(void) { /* Invert 6&7 for i82371 */ *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ outb(0x11,0xA0); outb(0x08,0xA1); outb(0x02,0xA1); outb(0x01,0xA1); outb(0xFF,0xA1); outb(0x11,0x20); outb(0x00,0x21); outb(0x04,0x21); outb(0x01,0x21); outb(0xFF,0x21); /* Finish writing the 82C59A PIC Operation Control Words */ outb(0x20,0xA0); outb(0x20,0x20); init_i8259a_irqs(); /* Not interested in the bogus interrupts (0,3,6), NMI (1), HALT (2), flash (5), or 21142 (8). */ init_pyxis_irqs(0x16f0000); common_init_isa_dma(); }
static void __init miata_init_irq(void) { if (alpha_using_srm) alpha_mv.device_interrupt = miata_srm_device_interrupt; #if 0 /* These break on MiataGL so we'll try not to do it at all. */ *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */ *(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */ #endif init_i8259a_irqs(); /* Not interested in the bogus interrupts (3,10), Fan Fault (0), NMI (1), or EIDE (9). We also disable the risers (4,5), since we don't know how to route the interrupts behind the bridge. */ init_pyxis_irqs(0x63b0000); common_init_isa_dma(); setup_irq(16+2, &halt_switch_irqaction); /* SRM only? */ setup_irq(16+6, &timer_cascade_irqaction); }
static void __init miata_init_irq(void) { if (alpha_using_srm) alpha_mv.device_interrupt = miata_srm_device_interrupt; #if 0 /* */ *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* */ *(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* */ #endif init_i8259a_irqs(); /* */ init_pyxis_irqs(0x63b0000); common_init_isa_dma(); setup_irq(16+2, &halt_switch_irqaction); /* */ setup_irq(16+6, &timer_cascade_irqaction); }
static void __init miata_init_irq(void) { if (alpha_using_srm) alpha_mv.device_interrupt = miata_srm_device_interrupt; init_i8259a_irqs(); /* Not interested in the bogus interrupts (3,10), Fan Fault (0), NMI (1), or EIDE (9). We also disable the risers (4,5), since we don't know how to route the interrupts behind the bridge. */ init_pyxis_irqs(0x63b0000); common_init_isa_dma(); setup_irq(16+2, &halt_switch_irqaction); /* SRM only? */ setup_irq(16+6, &timer_cascade_irqaction); }
static void __init sx164_init_irq(void) { outb(0, DMA1_RESET_REG); outb(0, DMA2_RESET_REG); outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; init_i8259a_irqs(); /* */ if (alpha_using_srm) init_srm_irqs(40, 0x3f0000); else init_pyxis_irqs(0xff00003f0000UL); setup_irq(16+6, &timer_cascade_irqaction); }
static void __init sx164_init_irq(void) { outb(0, DMA1_RESET_REG); outb(0, DMA2_RESET_REG); outb(DMA_MODE_CASCADE, DMA2_MODE_REG); outb(0, DMA2_MASK_REG); if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; init_i8259a_irqs(); /* Not interested in the bogus interrupts (0,3,4,5,40-47), NMI (1), or HALT (2). */ if (alpha_using_srm) init_srm_irqs(40, 0x3f0000); else init_pyxis_irqs(0xff00003f0000); setup_irq(16+6, &timer_cascade_irqaction); }