void
initialize_low_tracepoint (void)
{
#ifdef __powerpc64__
init_registers_powerpc_64l ();
init_registers_powerpc_altivec64l ();
init_registers_powerpc_cell64l ();
init_registers_powerpc_vsx64l ();
init_registers_powerpc_isa205_64l ();
init_registers_powerpc_isa205_altivec64l ();
init_registers_powerpc_isa205_vsx64l ();
init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
init_registers_powerpc_isa207_vsx64l ();
init_registers_powerpc_isa207_htm_vsx64l ();
#else
init_registers_powerpc_32l ();
init_registers_powerpc_altivec32l ();
init_registers_powerpc_cell32l ();
init_registers_powerpc_vsx32l ();
init_registers_powerpc_isa205_32l ();
init_registers_powerpc_isa205_altivec32l ();
init_registers_powerpc_isa205_vsx32l ();
init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
init_registers_powerpc_isa207_vsx32l ();
init_registers_powerpc_isa207_htm_vsx32l ();
init_registers_powerpc_e500l ();
#endif
}
static void
ppc_arch_setup (void)
{
#ifdef __powerpc64__
long msr;
/* On a 64-bit host, assume 64-bit inferior process with no
AltiVec registers. Reset ppc_hwcap to ensure that the
collect_register call below does not fail. */
init_registers_powerpc_64l ();
ppc_hwcap = 0;
/* Only if the high bit of the MSR is set, we actually have
a 64-bit inferior. */
collect_register_by_name ("msr", &msr);
if (msr < 0)
{
ppc_get_hwcap (&ppc_hwcap);
if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
{
/* Power ISA 2.05 (implemented by Power 6 and newer processors)
increases the FPSCR from 32 bits to 64 bits. Even though Power 7
supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05
set, only PPC_FEATURE_ARCH_2_06. Since for now the only bits
used in the higher half of the register are for Decimal Floating
Point, we check if that feature is available to decide the size
of the FPSCR. */
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
init_registers_powerpc_isa205_vsx64l ();
else
init_registers_powerpc_vsx64l ();
}
else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
{
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
init_registers_powerpc_isa205_altivec64l ();
else
init_registers_powerpc_altivec64l ();
}
return;
}
#endif
/* OK, we have a 32-bit inferior. */
init_registers_powerpc_32l ();
ppc_get_hwcap (&ppc_hwcap);
if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
{
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
init_registers_powerpc_isa205_vsx32l ();
else
init_registers_powerpc_vsx32l ();
}
else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
{
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
init_registers_powerpc_isa205_altivec32l ();
else
init_registers_powerpc_altivec32l ();
}
/* On 32-bit machines, check for SPE registers.
Set the low target's regmap field as appropriately. */
#ifndef __powerpc64__
the_low_target.regmap = ppc_regmap;
if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
{
init_registers_powerpc_e500l ();
the_low_target.regmap = ppc_regmap_e500;
}
/* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
slot and not just its second word. The PT_FPSCR supplied in a
32-bit GDB compilation doesn't reflect this. */
if (register_size (70) == 8)
ppc_regmap[70] = (48 + 2*32) * sizeof (long);
#endif
}
