void __init arch_init_irq(void)
{
unsigned int i;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
}
init_sb1250_irqs();
/*
* Map the high 16 bits of the mailbox registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
/* Clear the mailboxes. The firmware may leave them dirty */
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
/*
* Note that the timer interrupts are also mapped, but this is
* done in sb1250_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
}
void __init arch_init_irq(void)
{
unsigned int i;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
}
init_sb1250_irqs();
/*
* Map the high 16 bits of the mailbox registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
/* Clear the mailboxes. The firmware may leave them dirty */
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
__raw_writeq(tmp, IOAD
void __init arch_init_irq(void)
{
unsigned int i;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
}
init_sb1250_irqs();
/*
* Map the high 16 bits of the mailbox registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
/* Clear the mailboxes. The firmware may leave them dirty */
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
sb1250_steal_irq(K_INT_MBOX_0);
/*
* Note that the timer interrupts are also mapped, but this is
* done in sb1250_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
#ifdef CONFIG_KGDB
imask |= STATUSF_IP6;
#endif
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
#ifdef CONFIG_KGDB
if (kgdb_flag) {
kgdb_irq = K_INT_UART_0 + kgdb_port;
#ifdef CONFIG_SIBYTE_SB1250_DUART
sb1250_duart_present[kgdb_port] = 0;
#endif
/* Setup uart 1 settings, mapper */
__raw_writeq(M_DUART_IMR_BRK,
IOADDR(A_DUART_IMRREG(kgdb_port)));
sb1250_steal_irq(kgdb_irq);
__raw_writeq(IMR_IP6_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(kgdb_irq << 3)));
sb1250_unmask_irq(0, kgdb_irq);
}
#endif
}
