void clock_init(void) { u32 osc = clock_get_osc_bits(); /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ write32(&clk_rst->pllc_misc2, 0x2b << 17 | 0xb << 9); /* Max out the AVP clock before everything else (need PLLC for that). */ init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc, PLLC_MISC_LOCK_ENABLE); /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ write32(&clk_rst->clk_sys_rate, TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT); write32(&clk_rst->pllc_out, CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); write32(&clk_rst->sclk_brst_pol, /* sclk = 300 MHz */ SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); /* * Ambiguous quote from u-boot. TODO: what's this mean? * "should update same value in PMC_OSC_EDPD_OVER XOFS * field for warmboot " */ clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32(&clk_rst->pllp_outa, (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); write32(&clk_rst->pllp_outb, (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllx */ init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE); /* init pllu */ init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE); init_utmip_pll(); graphics_pll(); }
/** * The T124 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster */ void clock_init(void) { u32 val; u32 osc = clock_get_osc_bits(); /* * On poweron, AVP clock source (also called system clock) is set to * PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we * need to move the system clock's source to CLK_M temporarily. And * then switch it to PLLP_out4 (204MHz) at a later time. */ val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); writel(val, &clk_rst->sclk_brst_pol); udelay(2); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); /* Change the oscillator drive strength */ val = readl(&clk_rst->osc_ctrl); val &= ~OSC_XOFS_MASK; val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); writel(val, &clk_rst->osc_ctrl); /* Ambiguous quote from u-boot. TODO: what's this mean? * "should update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot "*/ val = readl(&pmc->osc_edpd_over); val &= ~PMC_OSC_EDPD_OVER_XOFS_MASK; val |= (OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); writel(val, &pmc->osc_edpd_over); /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ val = readl(&clk_rst->pllx_misc3); val &= ~PLLX_IDDQ_MASK; writel(val, &clk_rst->pllx_misc3); udelay(2); /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2); adjust_pllp_out_freqs(); init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx); init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc, osc_table[osc].pllp); init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc); init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld); init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu); init_utmip_pll(); val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); writel(val, &clk_rst->clk_sys_rate); }