Wire::Wire(double w_s, double s_s, enum Wire_placement wp, double resis, TechnologyParameter::DeviceType* dt) {
w_scale = w_s;
s_scale = s_s;
deviceType = dt;
wire_placement = wp;
resistivity = resis;
min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
in_rise_time = 0;
out_rise_time = 0;
switch (wire_placement) {
case outside_mat:
wire_width = g_tp.wire_outside_mat.pitch;
break;
case inside_mat :
wire_width = g_tp.wire_inside_mat.pitch;
break;
default:
wire_width = g_tp.wire_local.pitch;
break;
}
wire_spacing = wire_width;
wire_width *= (w_scale * 1e-6 / 2) /* (m) */;
wire_spacing *= (s_scale * 1e-6 / 2) /* (m) */;
init_wire();
wire_width_init = wire_width;
wire_spacing_init = wire_spacing;
assert(power.readOp.dynamic > 0);
assert(power.readOp.leakage > 0);
}
void
draw_wire(ModeInfo * mi)
{
int offset, i, j, found = 0;
unsigned char *z, *znew;
circuitstruct *wp;
if (circuits == NULL)
return;
wp = &circuits[MI_SCREEN(mi)];
if (wp->newcells == NULL)
return;
MI_IS_DRAWN(mi) = True;
/* wires do not grow so min max stuff does not change */
for (j = wp->minrow; j <= wp->maxrow; j++) {
for (i = wp->mincol; i <= wp->maxcol; i++) {
offset = j * wp->bncols + i;
z = wp->oldcells + offset;
znew = wp->newcells + offset;
if (*z != *znew) { /* Counting on once a space always a space */
found = 1;
*z = *znew;
if (!addtolist(mi, i - 2, j - 2, *znew - 1)) {
free_wire(MI_DISPLAY(mi), wp);
return;
}
}
}
}
for (i = 0; i < COLORS - 1; i++)
if (!draw_state(mi, i)) {
free_wire(MI_DISPLAY(mi), wp);
return;
}
if (++wp->generation > MI_CYCLES(mi) || !found) {
init_wire(mi);
return;
} else
do_gen(wp);
if (wp->redrawing) {
for (i = 0; i < REDRAWSTEP; i++) {
if ((*(wp->oldcells + wp->redrawpos))) {
drawCell(mi, wp->redrawpos % wp->bncols - 2,
wp->redrawpos / wp->bncols - 2, *(wp->oldcells + wp->redrawpos) - 1);
}
if (++(wp->redrawpos) >= wp->bncols * (wp->bnrows - 2)) {
wp->redrawing = 0;
break;
}
}
}
}
