int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; #ifdef CONFIG_VSC9953 int lane; int phy_addr; phy_interface_t phy_int; struct mii_dev *bus; #endif printf("Initializing Fman\n"); set_brdcfg9_for_gtx_clk(); initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); /* * Program on board RGMII PHY addresses. If the SGMII Riser * card used, we'll override the PHY address later. For any DTSEC that * is RGMII, we'll also override its PHY address later. We assume that * DTSEC4 and DTSEC5 are used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: fm_info_set_mdio(i, NULL); break; case PHY_INTERFACE_MODE_SGMII: t1040_handle_phy_interface_sgmii(i); break; case PHY_INTERFACE_MODE_RGMII: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ t1040_handle_phy_interface_rgmii(i); break; default: break; } } #ifdef CONFIG_VSC9953 for (i = 0; i < VSC9953_MAX_PORTS; i++) { lane = -1; phy_addr = 0; phy_int = PHY_INTERFACE_MODE_NONE; switch (i) { case 0: case 1: case 2: case 3: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A); /* PHYs connected over QSGMII */ if (lane >= 0) { phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i; phy_int = PHY_INTERFACE_MODE_QSGMII; break; } lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_SW1_MAC1 + i); if (lane < 0) break; /* PHYs connected over QSGMII */ if (i != 3 || lane_to_slot[lane] == 7) phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + i; else phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR; phy_int = PHY_INTERFACE_MODE_SGMII; break; case 4: case 5: case 6: case 7: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B); /* PHYs connected over QSGMII */ if (lane >= 0) { phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i - 4; phy_int = PHY_INTERFACE_MODE_QSGMII; break; } lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_SW1_MAC1 + i); /* PHYs connected over SGMII */ if (lane >= 0) { phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + i - 3; phy_int = PHY_INTERFACE_MODE_SGMII; } break; case 8: if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0) /* FM1@DTSEC1 is connected to SW1@PORT8 */ vsc9953_port_enable(i); break; case 9: if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { /* Enable L2 On MAC2 using SCFG */ struct ccsr_scfg *scfg = (struct ccsr_scfg *) CONFIG_SYS_MPC85xx_SCFG; out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | (0x80000000)); vsc9953_port_enable(i); } break; } if (lane >= 0) { bus = mii_dev_for_muxval(lane_to_slot[lane]); vsc9953_port_info_set_mdio(i, bus); vsc9953_port_enable(i); } vsc9953_port_info_set_phy_address(i, phy_addr); vsc9953_port_info_set_phy_int(i, phy_int); } #endif cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; struct mii_dev *bus; printf("Initializing Fman\n"); initialize_lane_to_slot(); /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); memset(mdio_mux, 0, sizeof(mdio_mux)); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_tgec_mdio_init(bis, &tgec_mdio_info); /* Register the three virtual MDIO front-ends */ hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); /* * Program the DTSEC PHY addresses assuming that they are all SGMII. * For any DTSEC that's RGMII, we'll override its PHY address later. * We assume that DTSEC5 is only used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; switch (slot) { case 1: /* Always DTSEC5 on Bank 3 */ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; hydra_mdio_set_mux("HYDRA_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: /* * If DTSEC4 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC5 is RGMII, * then it's routed via via EC2 to the second on-board * RGMII port. The other DTSECs cannot be routed to * RGMII. */ fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; hydra_mdio_set_mux("HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { slot = lane_to_slot[lane]; if (slot == 1) { /* XAUI card is in slot 1 */ clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, BRDCFG1_EMI2_SEL_SLOT1); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); } else { /* XAUI card is in slot 2 */ clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, BRDCFG1_EMI2_SEL_SLOT2); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); } } fm_info_set_mdio(FM1_10GEC1, miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; struct mii_dev *bus; int qsgmii; int phy_real_addr; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int srds_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; printf("Initializing Fman\n"); initialize_lane_to_slot(); /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); memset(mdio_mux, 0, sizeof(mdio_mux)); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_tgec_mdio_init(bis, &tgec_mdio_info); /* Register the three virtual MDIO front-ends */ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_RGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM1_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM2_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM3_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM1_TGEC_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM2_TGEC_MDIO"); /* * Program the DTSEC PHY addresses assuming that they are all SGMII. * For any DTSEC that's RGMII, we'll override its PHY address later. * We assume that DTSEC5 is only used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); #if (CONFIG_SYS_NUM_FMAN == 2) fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); #endif switch (srds_prtcl) { case 0: case 3: case 4: case 6: case 0x11: case 0x2a: case 0x34: case 0x36: fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); break; case 1: case 2: case 5: case 7: case 0x35: fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); break; default: printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); switch (slot) { case 1: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 3: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the * second on-board RGMII port. The other DTSECs cannot * be routed to RGMII. */ debug("FM1@DTSEC%u is RGMII at address %u\n", idx + 1, 0); fm_info_set_phy_address(i, 0); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); if (qsgmii) { for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) { phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; fm_info_set_phy_address(i, phy_real_addr); } } switch (srds_prtcl) { case 0x00: case 0x03: case 0x04: case 0x06: case 0x11: case 0x2a: case 0x34: case 0x36: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); break; case 0x01: case 0x02: case 0x05: case 0x07: case 0x35: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); break; default: break; } } /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } fm_info_set_mdio(FM1_10GEC1, miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); #if (CONFIG_SYS_NUM_FMAN == 2) for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { int idx = i - FM2_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; debug("FM2@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); switch (slot) { case 1: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 3: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { super_hydra_mdio_set_mux( "SUPER_HYDRA_FM3_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name( "SUPER_HYDRA_FM3_SGMII_MDIO")); } else { super_hydra_mdio_set_mux( "SUPER_HYDRA_FM2_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name( "SUPER_HYDRA_FM2_SGMII_MDIO")); } break; case PHY_INTERFACE_MODE_RGMII: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the * second on-board RGMII port. The other DTSECs cannot * be routed to RGMII. */ debug("FM2@DTSEC%u is RGMII at address %u\n", idx + 1, 1); fm_info_set_phy_address(i, 1); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman2: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM2); if (lane >= 0) { debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } fm_info_set_mdio(FM2_10GEC1, miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); #endif cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { case 0xd5: case 0xd6: /* QSGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, 0x8); fm_info_set_phy_address(FM1_DTSEC2, 0x9); fm_info_set_phy_address(FM1_DTSEC3, 0xa); fm_info_set_phy_address(FM1_DTSEC4, 0xb); break; case 0x95: case 0x99: /* * XFI does not need a PHY to work, but to avoid U-boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks the * XAUI card is used for the XFI MAC, which will cause error. */ fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6f: /* SGMII in Slot3, Slot4, Slot5 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x7f: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); break; case 0x47: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x77: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); break; case 0x5a: fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6a: fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x5b: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); break; case 0x6b: fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); break; default: break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_QSGMII: if (interface == PHY_INTERFACE_MODE_SGMII) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_2500_FM1_DTSEC1 + idx); } else { lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_FM1_A); } if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII2; else if (i == FM1_DTSEC4) mdio_mux[i] = EMI1_RGMII1; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: lane = serdes_get_first_lane(FSL_SRDS_1, XFI_FM1_MAC1 + idx); if (lane < 0) break; mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; struct memac_mdio_info tg_memac_mdio_info; unsigned int i; unsigned int serdes1_prtcl, serdes2_prtcl; int qsgmii; struct mii_dev *bus; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; if (!serdes1_prtcl) { printf("SERDES1 is not enabled\n"); return 0; } serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); serdes2_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; if (!serdes2_prtcl) { printf("SERDES2 is not enabled\n"); return 0; } serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); printf("Initializing Fman\n"); initialize_lane_to_slot(); memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); tg_memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_memac_mdio_init(bis, &tg_memac_mdio_info); /* * Program the two on board DTSEC PHY addresses assuming that they are * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and * 6 to on board SGMII phys */ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); switch (serdes1_prtcl) { case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n", CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #ifdef CONFIG_ARCH_B4420 case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n", CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); /* Fixing Serdes clock by programming FPGA register */ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); break; #endif default: printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; } switch (serdes2_prtcl) { case 0x17: case 0x18: debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); break; case 0x48: case 0x49: debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); break; case 0xb1: case 0xb2: case 0x8c: case 0x8d: debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); /* * XFI does not need a PHY to work, but to make U-Boot * happy, assign a fake PHY address for a XFI port. */ fm_info_set_phy_address(FM1_10GEC1, 0); fm_info_set_phy_address(FM1_10GEC2, 1); break; case 0x98: /* XAUI in Slot1 and Slot2 */ debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n", CONFIG_SYS_FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; case 0x9E: /* XAUI in Slot2 */ debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", CONFIG_SYS_FM1_10GEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC2, CONFIG_SYS_FM1_10GEC2_PHY_ADDR); break; default: printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); break; } /*set PHY address for QSGMII Riser Card on slot2*/ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM); if (qsgmii) { switch (serdes2_prtcl) { case 0xb2: case 0x8d: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); break; default: break; } } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { int idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: fm_info_set_mdio(i, miiphy_get_dev_by_name (DEFAULT_FM_TGEC_MDIO_NAME)); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: TGEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; printf("Initializing Fman\n"); initialize_lane_to_slot(); /* * Set TBIPA on FM1@DTSEC1. This is needed for configurations * where FM1@DTSEC1 isn't used directly, since it provides * MDIO for other ports. */ out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_tgec_mdio_init(bis, &tgec_mdio_info); /* * Program the three on-board SGMII PHY addresses. If the SGMII Riser * card used, we'll override the PHY address later. For any DTSEC that * is RGMII, we'll also override its PHY address later. We assume that * DTSEC4 and DTSEC5 are used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; if (slot) fm_info_set_phy_address(i, riser_phy_addr[i]); break; case PHY_INTERFACE_MODE_RGMII: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ fm_info_set_phy_address(i, i == FM1_DTSEC5 ? CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); break; } fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); } lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { slot = lane_to_slot[lane]; if (slot) fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); } fm_info_set_mdio(FM1_10GEC1, miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); #if defined(CONFIG_T2080QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); #endif t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); #if defined(CONFIG_T2081QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); #endif t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); else fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); switch (srds_s1) { case 0x1b: case 0x1c: case 0x95: case 0xa2: case 0x94: /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x50: case 0x51: case 0x5e: case 0x5f: case 0x64: case 0x65: /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x66: case 0x67: /* * XFI does not need a PHY to work, but to avoid U-boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks * the XAUI card is used for the XFI MAC, which will cause * error. */ fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); break; case 0x6a: case 0x6b: fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; case 0x6c: case 0x6d: fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x70: case 0x71: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; case 0xa6: case 0x8e: case 0x8f: case 0x82: case 0x83: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; case 0xa4: case 0x96: case 0x8a: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; #if defined(CONFIG_T2080QDS) case 0xd9: case 0xd3: case 0xcb: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); /* SGMII in Slot2 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; #elif defined(CONFIG_T2081QDS) case 0xca: case 0xcb: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); /* SGMII in Slot5 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); /* SGMII in Slot6 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); /* SGMII in Slot7 */ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); break; #endif case 0xf2: /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; default: break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { case 1: mdio_mux[i] = EMI1_SLOT1; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 2: mdio_mux[i] = EMI1_SLOT2; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; #if defined(CONFIG_T2081QDS) case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 6: mdio_mux[i] = EMI1_SLOT6; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; case 7: mdio_mux[i] = EMI1_SLOT7; fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; #endif } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4 || FM1_DTSEC10) mdio_mux[i] = EMI1_RGMII2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: if (srds_s1 == 0x51) { lane = serdes_get_first_lane(FSL_SRDS_1, XAUI_FM1_MAC9 + idx); } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { lane = serdes_get_first_lane(FSL_SRDS_1, HIGIG_FM1_MAC9 + idx); } else { if (i == FM1_10GEC1 || i == FM1_10GEC2) lane = serdes_get_first_lane(FSL_SRDS_1, XFI_FM1_MAC9 + idx); else lane = serdes_get_first_lane(FSL_SRDS_1, XFI_FM1_MAC1 + idx); } if (lane < 0) break; mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || (srds_s1 == 0x6a) || (srds_s1 == 0x70) || (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || (srds_s1 == 0x71)) { /* As XFI is in cage intead of a slot, so * ensure doesn't disable the corresponding port */ break; } slot = lane_to_slot[lane]; if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; printf("Initializing Fman\n"); set_brdcfg9_for_gtx_clk(); initialize_lane_to_slot(); /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); /* Register the muxing front-ends to the MDIO buses */ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); /* * Program on board RGMII PHY addresses. If the SGMII Riser * card used, we'll override the PHY address later. For any DTSEC that * is RGMII, we'll also override its PHY address later. We assume that * DTSEC4 and DTSEC5 are used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: break; case PHY_INTERFACE_MODE_SGMII: t1040_handle_phy_interface_sgmii(i); break; case PHY_INTERFACE_MODE_RGMII: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ t1040_handle_phy_interface_rgmii(i); break; default: break; } } cpu_eth_init(bis); #endif return pci_eth_init(bis); }