static u32 intc_active_irq(u32 cpu_irq)
{
u32 ret;
if (cpu_irq == CPU_EXTERNAL_IRQ) { /* armv7a IRQ */
ret = intc_read(INTC_SIR_IRQ);
/* Spurious IRQ ? */
if (ret & INTC_SIR_IRQ_SPURIOUSFLAG_M) {
return UINT_MAX;
}
ret = (ret & INTC_SIR_IRQ_ACTIVEIRQ_M);
if (intc_nrirq <= ret) {
return UINT_MAX;
}
} else if (cpu_irq == CPU_EXTERNAL_FIQ) { /* armv7a FIQ */
ret = intc_read(INTC_SIR_FIQ);
/* Spurious FIQ ? */
if (ret & INTC_SIR_FIQ_SPURIOUSFLAG_M) {
return UINT_MAX;
}
ret = (ret & INTC_SIR_FIQ_ACTIVEIRQ_M);
if (intc_nrirq <= ret) {
return UINT_MAX;
}
} else {
ret = UINT_MAX;
}
return ret;
}
int __init intc_init(physical_addr_t base, u32 nrirq)
{
u32 i, tmp;
intc_base = vmm_host_iomap(base, 0x1000);
intc_nrirq = nrirq;
tmp = intc_read(INTC_SYSCONFIG);
tmp |= INTC_SYSCONFIG_SOFTRST_M; /* soft reset */
intc_write(INTC_SYSCONFIG, tmp);
/* Wait for reset to complete */
while (!(intc_read(INTC_SYSSTATUS) &
INTC_SYSSTATUS_RESETDONE_M)) ;
/* Enable autoidle */
intc_write(INTC_SYSCONFIG, INTC_SYSCONFIG_AUTOIDLE_M);
/*
* Setup the Host IRQ subsystem.
*/
for (i = 0; i < intc_nrirq; i++) {
vmm_host_irq_set_chip(i, &intc_chip);
vmm_host_irq_set_handler(i, vmm_handle_fast_eoi);
}
/* Set active IRQ callback */
vmm_host_irq_set_active_callback(intc_active_irq);
return VMM_OK;
}
u32 intc_active_irq(u32 cpu_irq)
{
u32 ret = 0xFFFFFFFF;
if (cpu_irq == CPU_EXTERNAL_IRQ) { /* armv7a IRQ */
ret = intc_read(INTC_SIR_IRQ);
/* Spurious IRQ ? */
if(((u32) ret & INTC_SIR_IRQ_SPURIOUSFLAG_M)) {
ret = -1;
}
ret = ((u32) ret & INTC_SIR_IRQ_ACTIVEIRQ_M);
if (intc_nrirq <= ret) {
ret = -1;
}
} else if (cpu_irq == CPU_EXTERNAL_FIQ) { /* armv7a FIQ */
ret = intc_read(INTC_SIR_FIQ);
/* Spurious FIQ ? */
if(((u32) ret & INTC_SIR_FIQ_SPURIOUSFLAG_M)) {
ret = -1;
}
ret = ((u32) ret & INTC_SIR_FIQ_ACTIVEIRQ_M);
if (intc_nrirq <= ret) {
ret = -1;
}
}
return ret;
}
