C++ (Cpp) intel_update_microcode_from_cbfs示例

示例#1

文件： model_106cx_init.c 项目： punitvara/coreboot

static void model_106cx_init(struct device *cpu)
{
	char processor_name[49];

	/* Turn on caching if we haven't already */
	x86_enable_cache();

	/* Update the microcode */
	intel_update_microcode_from_cbfs();

	/* Print processor name */
	fill_processor_name(processor_name);
	printk(BIOS_INFO, "CPU: %s.\n", processor_name);

	/* Setup MTRRs */
	x86_setup_mtrrs();
	x86_mtrr_check();

	/* Enable the local CPU apics */
	setup_lapic();

	/* Enable virtualization */
	enable_vmx();

	/* Configure C States */
	configure_c_states();

	/* Configure Enhanced SpeedStep and Thermal Sensors */
	configure_misc();

	/* TODO: PIC thermal sensor control */

	/* Start up my CPU siblings */
	intel_sibling_init(cpu);
}

示例#2

文件： bootblock.c 项目： 0ida/coreboot

static void bootblock_cpu_init(void)
{
    /* Allow memory-mapped PCI config access. */
    setup_mmconfig();

    /* Load microcode before any caching. */
    intel_update_microcode_from_cbfs();
    enable_rom_caching();
}

示例#3

文件： bootblock.c 项目： AdriDlu/coreboot

static void bootblock_cpu_init(void)
{
	/* Check for Warm Reset */
	check_for_warm_reset();

	/* Load microcode before any caching. */
	intel_update_microcode_from_cbfs();

	enable_rom_caching();
	set_no_evict_mode_msr();
}

示例#4

文件： model_69x_init.c 项目： punitvara/coreboot

static void model_69x_init(struct device *dev)
{
	/* Turn on caching if we haven't already */
	x86_enable_cache();
	x86_setup_mtrrs();
	x86_mtrr_check();

	/* Update the microcode */
	intel_update_microcode_from_cbfs();

	/* Enable the local CPU apics */
	setup_lapic();
};

示例#5

文件： romstage.c 项目： af00/coreboot

asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
{
	void *top_of_stack;
	struct pei_data pei_data;
	struct romstage_params params = {
		.pei_data = &pei_data,
		.chipset_context = fih,
	};

	post_code(0x30);

	timestamp_add_now(TS_START_ROMSTAGE);

	/* Load microcode before RAM init */
	if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
		intel_update_microcode_from_cbfs();

	memset(&pei_data, 0, sizeof(pei_data));

	/* Display parameters */
	printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
		CONFIG_MMCONF_BASE_ADDRESS);
	printk(BIOS_INFO, "Using FSP 1.1\n");

	/* Display FSP banner */
	print_fsp_info(fih);

	/* Stash FSP version. */
	params.fsp_version = fsp_version(fih);

	/* Get power state */
	params.power_state = fill_power_state();

	/*
	 * Read and print board version.  Done after SOC romstage
	 * in case PCH needs to be configured to talk to the EC.
	 */
	if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
		printk(BIOS_INFO, "MLB: board version %d\n", board_id());

	/* Call into mainboard. */
	mainboard_romstage_entry(&params);
	soc_after_ram_init(&params);
	post_code(0x38);

	top_of_stack = setup_stack_and_mtrrs();

	printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
	timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
	return top_of_stack;
}

示例#6

文件： model_65x_init.c 项目： 0ida/coreboot

static void model_65x_init(device_t dev)
{
	/* Update the microcode */
	intel_update_microcode_from_cbfs();
	/* Initialize L2 cache */
	p6_configure_l2_cache();

	/* Turn on caching if we haven't already */
	x86_enable_cache();
	x86_setup_mtrrs();
	x86_mtrr_check();

	/* Enable the local cpu apics */
	setup_lapic();
};

示例#7

文件： model_f4x_init.c 项目： lynxis/coreboot-signed

static void model_f4x_init(struct device *cpu)
{
	/* Turn on caching if we haven't already */
	x86_enable_cache();

	if (!intel_ht_sibling()) {
		/* MTRRs are shared between threads */
		x86_setup_mtrrs();
		x86_mtrr_check();

		/* Update the microcode */
		intel_update_microcode_from_cbfs();
	}

	/* Enable the local CPU APICs */
	setup_lapic();

	/* Start up my CPU siblings */
	intel_sibling_init(cpu);
};

示例#8

文件： model_6bx_init.c 项目： Godkey/coreboot

static void model_6bx_init(device_t cpu)
{
    char processor_name[49];

    /* Turn on caching if we haven't already */
    x86_enable_cache();

    /* Update the microcode */
    intel_update_microcode_from_cbfs();

    /* Print processor name */
    fill_processor_name(processor_name);
    printk(BIOS_INFO, "CPU: %s.\n", processor_name);

    /* Setup MTRRs */
    x86_setup_mtrrs();
    x86_mtrr_check();

    /* Enable the local cpu apics */
    setup_lapic();
}

示例#9

文件： bootblock.c 项目： canistation/coreboot

static void bootblock_cpu_init(void)
{
	/* Load microcode before any caching. */
	intel_update_microcode_from_cbfs();
}