/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
startrtclock();
#if NBIOS32 > 0
bios32_init();
platform_init();
#endif
x86_64_proc0_tss_ldt_init();
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
#ifdef INTRDEBUG
intr_printconfig();
#endif
#if NIOAPIC > 0
ioapic_enable();
#endif
#ifdef MULTIPROCESSOR
cpu_init_idle_lwps();
#endif
spl0();
lcr8(0);
}
void
serial_intenable(void)
{
// Enable serial interrupts
if (serial_exists) {
pic_enable(IRQ_SERIAL);
ioapic_enable(IRQ_SERIAL);
}
}
void
console_init(void)
{
initlock(&console_lock, "console");
initlock(&input.lock, "console input");
devsw[CONSOLE].write = console_write;
devsw[CONSOLE].read = console_read;
use_console_lock = 1;
pic_enable(IRQ_KBD);
ioapic_enable(IRQ_KBD, 0);
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
#if NBIOS32 > 0
bios32_init();
#endif
x86_64_proc0_tss_ldt_init();
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
intr_printconfig();
#if NIOAPIC > 0
lapic_set_lvt();
ioapic_enable();
#endif
#ifdef MULTIPROCESSOR
cpu_init_idle_pcbs();
#endif
lcr8(0);
spl0();
cold = 0;
/*
* At this point the RNG is running, and if FSXR is set we can
* use it. Here we setup a periodic timeout to collect the data.
*/
if (viac3_rnd_present) {
timeout_set(&viac3_rnd_tmo, viac3_rnd, &viac3_rnd_tmo);
viac3_rnd(&viac3_rnd_tmo);
}
if (has_rdrand) {
timeout_set(&rdrand_tmo, rdrand, &rdrand_tmo);
rdrand(&rdrand_tmo);
}
#ifdef CRYPTO
/*
* Also, if the chip has crypto available, enable it.
*/
if (amd64_has_xcrypt)
viac3_crypto_setup();
if (amd64_has_aesni)
aesni_setup();
#endif
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
struct pcb *pcb;
startrtclock();
#if NBIOS32 > 0
bios32_init();
platform_init();
#endif
#ifdef PCIBIOS
pcibios_init();
#endif
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
#ifdef INTRDEBUG
intr_printconfig();
#endif
#if NIOAPIC > 0
ioapic_enable();
#endif
fpuinit(&cpu_info_primary);
/* resync cr0 after FPU configuration */
pcb = lwp_getpcb(&lwp0);
pcb->pcb_cr0 = rcr0() & ~CR0_TS;
#ifdef MULTIPROCESSOR
/* propagate this to the idle pcb's. */
cpu_init_idle_lwps();
#endif
spl0();
#if NLAPIC > 0
lapic_tpr = 0;
#endif
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
/*
* Note, on i386, configure is not running under splhigh unlike other
* architectures. This fact is used by the pcmcia irq line probing.
*/
gdt_init(); /* XXX - pcibios uses gdt stuff */
/* Set up proc0's TSS and LDT */
i386_proc0_tss_ldt_init();
#ifdef KVM86
kvm86_init();
#endif
if (config_rootfound("mainbus", NULL) == NULL)
panic("cpu_configure: mainbus not configured");
#if NIOAPIC > 0
if (nioapics > 0)
goto nomasks;
#endif
printf("biomask %x netmask %x ttymask %x\n", (u_short)IMASK(IPL_BIO),
(u_short)IMASK(IPL_NET), (u_short)IMASK(IPL_TTY));
#if NIOAPIC > 0
nomasks:
ioapic_enable();
#endif
proc0.p_addr->u_pcb.pcb_cr0 = rcr0();
#ifdef MULTIPROCESSOR
/* propagate TSS and LDT configuration to the idle pcb's. */
cpu_init_idle_pcbs();
#endif
spl0();
/*
* We can not know which is our root disk, defer
* until we can checksum blocks to figure it out.
*/
cold = 0;
/*
* At this point the RNG is running, and if FSXR is set we can
* use it. Here we setup a periodic timeout to collect the data.
*/
if (viac3_rnd_present) {
timeout_set(&viac3_rnd_tmo, viac3_rnd, &viac3_rnd_tmo);
viac3_rnd(&viac3_rnd_tmo);
}
#ifdef CRYPTO
/*
* Also, if the chip has crypto available, enable it.
*/
if (i386_has_xcrypt)
viac3_crypto_setup();
#endif
}
/*
* Attach the mainbus.
*/
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
union mainbus_attach_args mba;
#if defined(DOM0OPS) && defined(XEN3)
int numcpus = 0;
#ifdef MPBIOS
int mpbios_present = 0;
#endif
#if NACPI > 0 || defined(MPBIOS)
int numioapics = 0;
#endif
#endif /* defined(DOM0OPS) && defined(XEN3) */
aprint_naive("\n");
aprint_normal("\n");
#ifndef XEN3
memset(&mba.mba_caa, 0, sizeof(mba.mba_caa));
mba.mba_caa.cpu_number = 0;
mba.mba_caa.cpu_role = CPU_ROLE_SP;
mba.mba_caa.cpu_func = 0;
config_found_ia(self, "cpubus", &mba.mba_caa, mainbus_print);
#else /* XEN3 */
#ifdef DOM0OPS
if (xendomain_is_dom0()) {
#ifdef MPBIOS
mpbios_present = mpbios_probe(self);
#endif
#if NPCI > 0
/* ACPI needs to be able to access PCI configuration space. */
pci_mode = pci_mode_detect();
#ifdef PCI_BUS_FIXUP
pci_maxbus = pci_bus_fixup(NULL, 0);
aprint_debug_dev(self, "PCI bus max, after pci_bus_fixup: %i\n",
pci_maxbus);
#ifdef PCI_ADDR_FIXUP
pciaddr.extent_port = NULL;
pciaddr.extent_mem = NULL;
pci_addr_fixup(NULL, pci_maxbus);
#endif /* PCI_ADDR_FIXUP */
#endif /* PCI_BUS_FIXUP */
#if NACPI > 0
acpi_present = acpi_probe();
if (acpi_present)
mpacpi_active = mpacpi_scan_apics(self,
&numcpus, &numioapics);
if (!mpacpi_active)
#endif
{
#ifdef MPBIOS
if (mpbios_present)
mpbios_scan(self, &numcpus, &numioapics);
else
#endif
if (numcpus == 0) {
memset(&mba.mba_caa, 0, sizeof(mba.mba_caa));
mba.mba_caa.cpu_number = 0;
mba.mba_caa.cpu_role = CPU_ROLE_SP;
mba.mba_caa.cpu_func = 0;
config_found_ia(self, "cpubus",
&mba.mba_caa, mainbus_print);
}
}
#if NIOAPIC > 0
ioapic_enable();
#endif
#endif /* NPCI */
}
#endif /* DOM0OPS */
#endif /* XEN3 */
#if NIPMI > 0
memset(&mba.mba_ipmi, 0, sizeof(mba.mba_ipmi));
mba.mba_ipmi.iaa_iot = X86_BUS_SPACE_IO;
mba.mba_ipmi.iaa_memt = X86_BUS_SPACE_MEM;
if (ipmi_probe(&mba.mba_ipmi))
config_found_ia(self, "ipmibus", &mba.mba_ipmi, 0);
#endif
#if NHYPERVISOR > 0
mba.mba_haa.haa_busname = "hypervisor";
config_found_ia(self, "hypervisorbus", &mba.mba_haa, mainbus_print);
#endif
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
/*
* Note, on i386, configure is not running under splhigh unlike other
* architectures. This fact is used by the pcmcia irq line probing.
*/
gdt_init(); /* XXX - pcibios uses gdt stuff */
/* Set up proc0's TSS */
i386_proc0_tss_init();
#ifdef KVM86
kvm86_init();
#endif
pmap_bootstrap_pae();
#if defined(MULTIPROCESSOR) || \
(NACPI > 0 && !defined(SMALL_KERNEL))
/* install the lowmem ptp after boot args for 1:1 mappings */
pmap_prealloc_lowmem_ptp();
#endif
#ifdef MULTIPROCESSOR
pmap_kenter_pa((vaddr_t)MP_TRAMPOLINE, /* virtual */
(paddr_t)MP_TRAMPOLINE, /* physical */
PROT_READ | PROT_WRITE | PROT_EXEC); /* protection */
pmap_kenter_pa((vaddr_t)MP_TRAMP_DATA, /* virtual */
(paddr_t)MP_TRAMP_DATA, /* physical */
PROT_READ | PROT_WRITE); /* protection */
#endif
if (config_rootfound("mainbus", NULL) == NULL)
panic("cpu_configure: mainbus not configured");
#if NIOAPIC > 0
ioapic_enable();
#endif
proc0.p_addr->u_pcb.pcb_cr0 = rcr0();
#ifdef MULTIPROCESSOR
/* propagate TSS configuration to the idle pcb's. */
cpu_init_idle_pcbs();
#endif
spl0();
/*
* We can not know which is our root disk, defer
* until we can checksum blocks to figure it out.
*/
cold = 0;
/*
* At this point the RNG is running, and if FSXR is set we can
* use it. Here we setup a periodic timeout to collect the data.
*/
if (viac3_rnd_present) {
timeout_set(&viac3_rnd_tmo, viac3_rnd, &viac3_rnd_tmo);
viac3_rnd(&viac3_rnd_tmo);
}
if (has_rdrand || has_rdseed) {
timeout_set(&rdrand_tmo, rdrand, &rdrand_tmo);
rdrand(&rdrand_tmo);
}
#ifdef CRYPTO
/*
* Also, if the chip has crypto available, enable it.
*/
if (i386_has_xcrypt)
viac3_crypto_setup();
#endif
}