/**
* \brief Run low power demo
*
* This function initializes the XMEGA to the least power consuming state,
* before initializing the sleep manager interrupts on switchports.
* The device is then put to sleep, and the sleep mode is configured by the
* interrupt routines.
*/
int main(void)
{
board_init();
sysclk_init();
lowpower_init();
/* Initialize the sleep manager. */
sleepmgr_init();
/* Enable interrupts from switchports on
* low level to sense all interrupts */
pmic_init();
SWITCHPORT0.INTCTRL = SWITCHPORT_INT_LEVEL;
SWITCHPORT1.INTCTRL = SWITCHPORT_INT_LEVEL;
SWITCHPORT0.INT0MASK = SWITCHMASK0;
SWITCHPORT1.INT0MASK = SWITCHMASK1;
ioport_configure_port_pin(&SWITCHPORT0,
SWITCHMASK0, IOPORT_LEVEL | IOPORT_PULL_UP);
ioport_configure_port_pin(&SWITCHPORT1,
SWITCHMASK1, IOPORT_LEVEL | IOPORT_PULL_UP);
cpu_irq_enable();
/* Start in active mode */
sleepmgr_lock_mode(SLEEPMGR_ACTIVE);
/* Go to sleep, sleep modes are configured by interrupt routines. */
while (1) {
sleepmgr_enter_sleep();
}
}
/**
* Initialize tracing on A3BU
*/
void a3bu_trace_init() {
ioport_configure_port_pin(&PORTB, PIN0_bm, IOPORT_DIR_OUTPUT);
ioport_configure_port_pin(&PORTB, PIN1_bm, IOPORT_DIR_OUTPUT);
ioport_configure_port_pin(&PORTB, PIN2_bm, IOPORT_DIR_OUTPUT);
ioport_configure_port_pin(&PORTB, PIN3_bm, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(SPIN_0, 0);
}
static bool spi_init_pins(void)
{
ioport_configure_port_pin(&PORTC, PIN4_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
//ioport_configure_port_pin(&PORTC, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT);
ioport_configure_port_pin(&PORTC, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
ioport_configure_port_pin(&PORTC, PIN6_bm, IOPORT_DIR_INPUT);
ioport_configure_port_pin(&PORTC, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
return 0;
}
/**
* \brief Test physical loop-back with some characters in sunc mode.
*
* This function sends a character over USART on loop back to verify that init
* and sending/receiving works. A jumper is connected on the USART.
*
* \param test Current test case.
*/
static void run_loopback_syncmode_test(const struct test_case *test)
{
uint8_t out_c = 'c';
uint8_t in_c = 0;
port_pin_t sck_pin;
sysclk_enable_module(POWER_RED_REG0, PRUSART0_bm);
usart_set_mode(&CONF_UNIT_USART, USART_CMODE_SYNCHRONOUS_gc);
sck_pin = IOPORT_CREATE_PIN(PORTE, 2);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH );
usart_spi_set_baudrate(&CONF_UNIT_USART, CONF_UNIT_BAUDRATE,
sysclk_get_source_clock_hz());
usart_tx_enable(&CONF_UNIT_USART);
usart_rx_enable(&CONF_UNIT_USART);
usart_putchar(&CONF_UNIT_USART, out_c);
in_c = usart_getchar(&CONF_UNIT_USART);
test_assert_true(test, in_c == out_c,
"Read character through sync mode is not correct: %d != %d", in_c, out_c);
}
/**
* \brief Initialize USART in SPI master mode.
*
* This function initializes the USART module in SPI master mode using the
* usart_spi_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*/
void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt)
{
usart->UBRR = 0;
usart_enable_module_clock(usart);
usart_set_mode(usart, USART_CMODE_MSPI_gc);
port_pin_t sck_pin;
#ifdef USARTA0
if ((uintptr_t)usart == (uintptr_t)&UCSR0A) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 2);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH );
}
#endif
#ifdef USARTA1
if ((uintptr_t)usart == (uintptr_t)&UCSR1A) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH );
}
#endif
if (opt->spimode == 1 || opt->spimode == 3) {
usart->UCSRnC |= USART_UCPHA_bm;
} else {
usart->UCSRnC &= ~USART_UCPHA_bm;
}
if (opt->spimode == 2 || opt->spimode == 3) {
usart->UCSRnC |= USART_UCPOL_bm;
} else {
usart->UCSRnC &= ~USART_UCPOL_bm;
}
if (opt->data_order) {
usart->UCSRnC |= USART_DORD_bm;
} else {
usart->UCSRnC &= ~USART_DORD_bm;
}
usart_spi_set_baudrate(usart, opt->baudrate,
sysclk_get_source_clock_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
}
void Radio_Init()
{
transmit_lock = 0;
// disable radio during config
ioport_set_pin_low (CE);
/* IRQ */
// Enable radio interrupt. This interrupt is triggered when data are received and when a transmission completes.
ioport_configure_port_pin(&PORTC, PIN2_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT | IOPORT_SENSE_FALLING);
PORTC.INT0MASK = PIN2_bm;
PORTC.INTCTRL = PORT_INT0LVL_LO_gc;
PMIC.CTRL |= PMIC_LOLVLEN_bm;
/* CE */
ioport_configure_port_pin(&PORTC, PIN3_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
// A 10.3 ms delay is required between power off and power on states (controlled by 3.3 V supply).
_delay_ms(11);
/* Set up SPI */
/* Slave select */
ioport_configure_port_pin(&PORTC, PIN4_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
/* MOSI, MISO, SCK */
ioport_configure_port_pin(&PORTC, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
ioport_configure_port_pin(&PORTC, PIN6_bm, IOPORT_DIR_INPUT);
ioport_configure_port_pin(&PORTC, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
spi_master_init(&SPID);
spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0);
spi_enable(&SPID);
// Configure the radio registers that are not application-dependent.
configure_registers();
// A 1.5 ms delay is required between power down and power up states (controlled by PWR_UP bit in CONFIG)
_delay_ms(2);
// enable radio as a receiver
ioport_set_pin_high (CE);
}
/**
* \brief Initialize low power mode
*
* Disconnect all peripherals, enable pull-up on all I/O pins, disable watchdog
* timer and brown out detection, and JTAG-interface (if configured in
* \ref conf_low_power_demo.h )
*/
static void lowpower_init(void)
{
/* Disable unused modules */
sysclk_disable_peripheral_clock(&AES);
sysclk_disable_peripheral_clock(&DMA);
sysclk_disable_peripheral_clock(&EVSYS);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&RTC);
sysclk_disable_peripheral_clock(&EBI);
#endif
/* Disable TWI */
sysclk_disable_peripheral_clock(&TWIC);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&TWID);
#endif
sysclk_disable_peripheral_clock(&TWIE);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&TWIF);
#endif
/* Disable SPI */
sysclk_disable_peripheral_clock(&SPIC);
sysclk_disable_peripheral_clock(&SPID);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&SPIF);
#endif
/* Disable USART */
sysclk_disable_peripheral_clock(&USARTC0);
sysclk_disable_peripheral_clock(&USARTC1);
sysclk_disable_peripheral_clock(&USARTD0);
sysclk_disable_peripheral_clock(&USARTD1);
sysclk_disable_peripheral_clock(&USARTE0);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&USARTE1);
#endif
sysclk_disable_peripheral_clock(&USARTF0);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&USARTF1);
#endif
/* Disable timers/counters */
sysclk_disable_peripheral_clock(&TCC0);
sysclk_disable_peripheral_clock(&TCC1);
sysclk_disable_peripheral_clock(&TCD0);
sysclk_disable_peripheral_clock(&TCD1);
sysclk_disable_peripheral_clock(&TCE0);
sysclk_disable_peripheral_clock(&TCE1);
sysclk_disable_peripheral_clock(&TCF0);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&TCF1);
#endif
/* Disable HIRES */
sysclk_disable_peripheral_clock(&HIRESC);
sysclk_disable_peripheral_clock(&HIRESD);
sysclk_disable_peripheral_clock(&HIRESE);
sysclk_disable_peripheral_clock(&HIRESF);
/* Disable analog modules */
sysclk_disable_peripheral_clock(&ACA);
sysclk_disable_peripheral_clock(&ADCA);
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
sysclk_disable_peripheral_clock(&DACA);
#endif
sysclk_disable_peripheral_clock(&ACB);
sysclk_disable_peripheral_clock(&ADCB);
sysclk_disable_peripheral_clock(&DACB);
/* Enable pull-up on all I/O pins */
ioport_configure_port_pin(&PORTA, 0xF4,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTA,
0x03, IOPORT_DIR_INPUT | IOPORT_INPUT_DISABLE);
ioport_configure_port_pin(&PORTB, 0x7F,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTC, 0xFF,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTD, 0x3F,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTE, 0x0F,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTF, 0xFF,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTR, 0x03,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
#if AVR8_PART_IS_DEFINED(ATxmega256A3BU)
/* Disable display for A3BU Xplained */
ioport_configure_pin(NHD_C12832A1Z_RESETN, IOPORT_DIR_INPUT);
#endif
#if AVR8_PART_IS_DEFINED(ATxmega128A1)
ioport_configure_port_pin(&PORTH, 0xFF,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTJ, 0xFF,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTK, 0xFF,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
ioport_configure_port_pin(&PORTQ, 0x0F,
IOPORT_DIR_INPUT | IOPORT_PULL_UP);
#endif
/* Disable Watchdog timer */
wdt_disable();
/* Enable EEPROM and Flash power reduction mode. */
ccp_write_io((uint8_t *)&NVM.CTRLB, NVM_EPRM_bm | NVM_FPRM_bm);
#ifdef NO_JTAG
ccp_write_io((uint8_t *)&MCU.MCUCR, MCU_JTAGD_bm);
#endif
}
/**
* \brief Initialize USART in SPI master mode.
*
* This function initializes the USART module in SPI master mode using the
* usart_spi_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*/
void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt)
{
usart_enable_module_clock(usart);
usart_set_mode(usart, USART_CMODE_MSPI_gc);
port_pin_t sck_pin;
if (opt->spimode == 1 || opt->spimode == 3) {
//! \todo Fix when UCPHA_bm is added to header file.
usart->CTRLC |= 0x02;
} else {
//! \todo Fix when UCPHA_bm is added to header file.
usart->CTRLC &= ~0x02;
}
// configure Clock polarity using INVEN bit of the correct SCK I/O port
if (opt->spimode == 2 || opt->spimode == 3) {
#ifdef USARTC0
if ((uint16_t)usart == (uint16_t)&USARTC0) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTC1
if ((uint16_t)usart == (uint16_t)&USARTC1) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTD0
if ((uint16_t)usart == (uint16_t)&USARTD0) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTD1
if ((uint16_t)usart == (uint16_t)&USARTD1) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTE0
if ((uint16_t)usart == (uint16_t)&USARTE0) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTE1
if ((uint16_t)usart == (uint16_t)&USARTE1) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTF0
if ((uint16_t)usart == (uint16_t)&USARTF0) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 1);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
#ifdef USARTF1
if ((uint16_t)usart == (uint16_t)&USARTF1) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 5);
ioport_configure_port_pin(ioport_pin_to_port(sck_pin),
ioport_pin_to_mask(sck_pin),
IOPORT_DIR_OUTPUT | IOPORT_INIT_HIGH | IOPORT_INV_ENABLED);
}
#endif
}
usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
}
