static int __init nvic_of_init(struct device_node *node,
struct device_node *parent)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
unsigned int irqs, i, ret, numbanks;
void __iomem *nvic_base;
numbanks = (readl_relaxed(V7M_SCS_ICTR) &
V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
nvic_base = of_iomap(node, 0);
if (!nvic_base) {
pr_warn("unable to map nvic registers\n");
return -ENOMEM;
}
irqs = numbanks * 32;
if (irqs > NVIC_MAX_IRQ)
irqs = NVIC_MAX_IRQ;
nvic_irq_domain =
irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
if (!nvic_irq_domain) {
pr_warn("Failed to allocate irq domain\n");
return -ENOMEM;
}
ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
"nvic_irq", handle_fasteoi_irq,
clr, 0, IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_warn("Failed to allocate irq chips\n");
irq_domain_remove(nvic_irq_domain);
return ret;
}
for (i = 0; i < numbanks; ++i) {
struct irq_chip_generic *gc;
gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
gc->reg_base = nvic_base + 4 * i;
gc->chip_types[0].regs.enable = NVIC_ISER;
gc->chip_types[0].regs.disable = NVIC_ICER;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
gc->chip_types[0].chip.irq_eoi = nvic_eoi;
/* disable interrupts */
writel_relaxed(~0, gc->reg_base + NVIC_ICER);
}
/* Set priority on all interrupts */
for (i = 0; i < irqs; i += 4)
writel_relaxed(0, nvic_base + NVIC_IPR + i);
return 0;
}
static int __init moxart_of_intc_init(struct device_node *node,
struct device_node *parent)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
int ret;
struct irq_chip_generic *gc;
intc.base = of_iomap(node, 0);
if (!intc.base) {
pr_err("%s: unable to map IC registers\n",
node->full_name);
return -EINVAL;
}
intc.domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
intc.base);
if (!intc.domain) {
pr_err("%s: unable to create IRQ domain\n", node->full_name);
return -EINVAL;
}
ret = irq_alloc_domain_generic_chips(intc.domain, 32, 1,
"MOXARTINTC", handle_edge_irq,
clr, 0, IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_err("%s: could not allocate generic chip\n",
node->full_name);
irq_domain_remove(intc.domain);
return -EINVAL;
}
ret = of_property_read_u32(node, "interrupt-mask",
&intc.interrupt_mask);
if (ret)
pr_err("%s: could not read interrupt-mask DT property\n",
node->full_name);
gc = irq_get_domain_generic_chip(intc.domain, 0);
gc->reg_base = intc.base;
gc->chip_types[0].regs.mask = IRQ_MASK_REG;
gc->chip_types[0].regs.ack = IRQ_CLEAR_REG;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
writel(0, intc.base + IRQ_MASK_REG);
writel(0xffffffff, intc.base + IRQ_CLEAR_REG);
writel(intc.interrupt_mask, intc.base + IRQ_MODE_REG);
writel(intc.interrupt_mask, intc.base + IRQ_LEVEL_REG);
set_handle_irq(handle_irq);
return 0;
}
static int __init orion_irq_init(struct device_node *np,
struct device_node *parent)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
int n, ret, base, num_chips = 0;
struct resource r;
/* count number of irq chips by valid reg addresses */
while (of_address_to_resource(np, num_chips, &r) == 0)
num_chips++;
orion_irq_domain = irq_domain_add_linear(np,
num_chips * ORION_IRQS_PER_CHIP,
&irq_generic_chip_ops, NULL);
if (!orion_irq_domain)
panic("%s: unable to add irq domain\n", np->name);
ret = irq_alloc_domain_generic_chips(orion_irq_domain,
ORION_IRQS_PER_CHIP, 1, np->name,
handle_level_irq, clr, 0,
IRQ_GC_INIT_MASK_CACHE);
if (ret)
panic("%s: unable to alloc irq domain gc\n", np->name);
for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) {
struct irq_chip_generic *gc =
irq_get_domain_generic_chip(orion_irq_domain, base);
of_address_to_resource(np, n, &r);
if (!request_mem_region(r.start, resource_size(&r), np->name))
panic("%s: unable to request mem region %d",
np->name, n);
gc->reg_base = ioremap(r.start, resource_size(&r));
if (!gc->reg_base)
panic("%s: unable to map resource %d", np->name, n);
gc->chip_types[0].regs.mask = ORION_IRQ_MASK;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
/* mask all interrupts */
writel(0, gc->reg_base + ORION_IRQ_MASK);
}
set_handle_irq(orion_handle_irq);
return 0;
}
static int __init digicolor_of_init(struct device_node *node,
struct device_node *parent)
{
static void __iomem *reg_base;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct regmap *ucregs;
int ret;
reg_base = of_iomap(node, 0);
if (!reg_base) {
pr_err("%s: unable to map IC registers\n", node->full_name);
return -ENXIO;
}
/* disable all interrupts */
writel(0, reg_base + IC_INT0ENABLE_LO);
writel(0, reg_base + IC_INT0ENABLE_XLO);
ucregs = syscon_regmap_lookup_by_phandle(node, "syscon");
if (IS_ERR(ucregs)) {
pr_err("%s: unable to map UC registers\n", node->full_name);
return PTR_ERR(ucregs);
}
/* channel 1, regular IRQs */
regmap_write(ucregs, UC_IRQ_CONTROL, 1);
digicolor_irq_domain =
irq_domain_add_linear(node, 64, &irq_generic_chip_ops, NULL);
if (!digicolor_irq_domain) {
pr_err("%s: unable to create IRQ domain\n", node->full_name);
return -ENOMEM;
}
ret = irq_alloc_domain_generic_chips(digicolor_irq_domain, 32, 1,
"digicolor_irq", handle_level_irq,
clr, 0, 0);
if (ret) {
pr_err("%s: unable to allocate IRQ gc\n", node->full_name);
return ret;
}
digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO);
digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO);
set_handle_irq(digicolor_handle_irq);
return 0;
}
static __init void
sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
int ret;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
gc->reg_base = base;
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
}
static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
{
int ret;
int i;
ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
IRQ_LEVEL, 0);
if (ret) {
pr_warn("Failed to allocate irq chips\n");
return ret;
}
for (i = 0; i < omap_nr_pending; i++) {
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_get_domain_generic_chip(d, 32 * i);
gc->reg_base = base;
ct = gc->chip_types;
ct->type = IRQ_TYPE_LEVEL_MASK;
ct->handler = handle_level_irq;
ct->chip.irq_ack = omap_mask_ack_irq;
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
ct->regs.disable = INTC_MIR_SET0 + 32 * i;
}
return 0;
}
static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
{
struct device_node *np = info->node;
struct device *dev = info->priv->dev;
struct tz1090_gpio_bank *bank;
struct irq_chip_generic *gc;
int err;
bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
if (!bank) {
dev_err(dev, "unable to allocate driver data\n");
return -ENOMEM;
}
/* Offset the main registers to the first register in this bank */
bank->reg = info->priv->reg + info->index * 4;
/* Set up GPIO chip */
snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u",
info->index);
bank->chip.label = bank->label;
bank->chip.dev = dev;
bank->chip.direction_input = tz1090_gpio_direction_input;
bank->chip.direction_output = tz1090_gpio_direction_output;
bank->chip.get = tz1090_gpio_get;
bank->chip.set = tz1090_gpio_set;
bank->chip.free = tz1090_gpio_free;
bank->chip.request = tz1090_gpio_request;
bank->chip.to_irq = tz1090_gpio_to_irq;
bank->chip.of_node = np;
/* GPIO numbering from 0 */
bank->chip.base = info->index * 30;
bank->chip.ngpio = 30;
/* Add the GPIO bank */
gpiochip_add(&bank->chip);
/* Get the GPIO bank IRQ if provided */
bank->irq = irq_of_parse_and_map(np, 0);
/* The interrupt is optional (it may be used by another core on chip) */
if (!bank->irq) {
dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
info->index);
return 0;
}
dev_info(dev, "Setting up IRQs for GPIO bank %u\n",
info->index);
/*
* Initialise all interrupts to disabled so we don't get
* spurious ones on a dirty boot and hit the BUG_ON in the
* handler.
*/
tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0);
/* Add a virtual IRQ for each GPIO */
bank->domain = irq_domain_add_linear(np,
bank->chip.ngpio,
&irq_generic_chip_ops,
bank);
/* Set up a generic irq chip with 2 chip types (level and edge) */
err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2,
bank->label, handle_bad_irq, 0, 0,
IRQ_GC_INIT_NESTED_LOCK);
if (err) {
dev_info(dev,
"irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n",
info->index);
irq_domain_remove(bank->domain);
return 0;
}
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg;
/* level chip type */
gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
gc->chip_types[0].handler = handle_level_irq;
gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS;
gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN;
gc->chip_types[0].chip.irq_startup = gpio_startup_irq;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type;
gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake;
gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
/* edge chip type */
gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
gc->chip_types[1].handler = handle_edge_irq;
gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS;
gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN;
gc->chip_types[1].chip.irq_startup = gpio_startup_irq;
gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit;
gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type;
gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake;
gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
/* Setup chained handler for this GPIO bank */
irq_set_handler_data(bank->irq, bank);
irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler);
return 0;
}
static int tb10x_gpio_probe(struct platform_device *pdev)
{
struct tb10x_gpio *tb10x_gpio;
struct resource *mem;
struct device_node *dn = pdev->dev.of_node;
int ret = -EBUSY;
u32 ngpio;
if (!dn)
return -EINVAL;
if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
return -EINVAL;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem) {
dev_err(&pdev->dev, "No memory resource defined.\n");
return -EINVAL;
}
tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
if (tb10x_gpio == NULL)
return -ENOMEM;
spin_lock_init(&tb10x_gpio->spinlock);
tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(tb10x_gpio->base))
return PTR_ERR(tb10x_gpio->base);
tb10x_gpio->gc.label = of_node_full_name(dn);
tb10x_gpio->gc.dev = &pdev->dev;
tb10x_gpio->gc.owner = THIS_MODULE;
tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
tb10x_gpio->gc.get = tb10x_gpio_get;
tb10x_gpio->gc.direction_output = tb10x_gpio_direction_out;
tb10x_gpio->gc.set = tb10x_gpio_set;
tb10x_gpio->gc.request = tb10x_gpio_request;
tb10x_gpio->gc.free = tb10x_gpio_free;
tb10x_gpio->gc.base = -1;
tb10x_gpio->gc.ngpio = ngpio;
tb10x_gpio->gc.can_sleep = false;
ret = gpiochip_add(&tb10x_gpio->gc);
if (ret < 0) {
dev_err(&pdev->dev, "Could not add gpiochip.\n");
goto fail_gpiochip_registration;
}
platform_set_drvdata(pdev, tb10x_gpio);
if (of_find_property(dn, "interrupt-controller", NULL)) {
struct irq_chip_generic *gc;
ret = platform_get_irq(pdev, 0);
if (ret < 0) {
dev_err(&pdev->dev, "No interrupt specified.\n");
goto fail_get_irq;
}
tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
tb10x_gpio->irq = ret;
ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
IRQF_TRIGGER_NONE | IRQF_SHARED,
dev_name(&pdev->dev), tb10x_gpio);
if (ret != 0)
goto fail_request_irq;
tb10x_gpio->domain = irq_domain_add_linear(dn,
tb10x_gpio->gc.ngpio,
&irq_generic_chip_ops, NULL);
if (!tb10x_gpio->domain) {
ret = -ENOMEM;
goto fail_irq_domain;
}
ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
IRQ_GC_INIT_MASK_CACHE);
if (ret)
goto fail_irq_domain;
gc = tb10x_gpio->domain->gc->gc[0];
gc->reg_base = tb10x_gpio->base;
gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
}
return 0;
fail_irq_domain:
fail_request_irq:
fail_get_irq:
gpiochip_remove(&tb10x_gpio->gc);
fail_gpiochip_registration:
fail_ioremap:
return ret;
}
static int pdc_intc_probe(struct platform_device *pdev)
{
struct pdc_intc_priv *priv;
struct device_node *node = pdev->dev.of_node;
struct resource *res_regs;
struct irq_chip_generic *gc;
unsigned int i;
int irq, ret;
u32 val;
if (!node)
return -ENOENT;
/* Get registers */
res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res_regs == NULL) {
dev_err(&pdev->dev, "cannot find registers resource\n");
return -ENOENT;
}
/* Allocate driver data */
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
dev_err(&pdev->dev, "cannot allocate device data\n");
return -ENOMEM;
}
raw_spin_lock_init(&priv->lock);
platform_set_drvdata(pdev, priv);
/* Ioremap the registers */
priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start,
res_regs->end - res_regs->start);
if (!priv->pdc_base)
return -EIO;
/* Get number of peripherals */
ret = of_property_read_u32(node, "num-perips", &val);
if (ret) {
dev_err(&pdev->dev, "No num-perips node property found\n");
return -EINVAL;
}
if (val > SYS0_HWIRQ) {
dev_err(&pdev->dev, "num-perips (%u) out of range\n", val);
return -EINVAL;
}
priv->nr_perips = val;
/* Get number of syswakes */
ret = of_property_read_u32(node, "num-syswakes", &val);
if (ret) {
dev_err(&pdev->dev, "No num-syswakes node property found\n");
return -EINVAL;
}
if (val > SYS0_HWIRQ) {
dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val);
return -EINVAL;
}
priv->nr_syswakes = val;
/* Get peripheral IRQ numbers */
priv->perip_irqs = devm_kzalloc(&pdev->dev, 4 * priv->nr_perips,
GFP_KERNEL);
if (!priv->perip_irqs) {
dev_err(&pdev->dev, "cannot allocate perip IRQ list\n");
return -ENOMEM;
}
for (i = 0; i < priv->nr_perips; ++i) {
irq = platform_get_irq(pdev, 1 + i);
if (irq < 0) {
dev_err(&pdev->dev, "cannot find perip IRQ #%u\n", i);
return irq;
}
priv->perip_irqs[i] = irq;
}
/* check if too many were provided */
if (platform_get_irq(pdev, 1 + i) >= 0) {
dev_err(&pdev->dev, "surplus perip IRQs detected\n");
return -EINVAL;
}
/* Get syswake IRQ number */
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "cannot find syswake IRQ\n");
return irq;
}
priv->syswake_irq = irq;
/* Set up an IRQ domain */
priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops,
priv);
if (unlikely(!priv->domain)) {
dev_err(&pdev->dev, "cannot add IRQ domain\n");
return -ENOMEM;
}
/*
* Set up 2 generic irq chips with 2 chip types.
* The first one for peripheral irqs (only 1 chip type used)
* The second one for syswake irqs (edge and level chip types)
*/
ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc",
handle_level_irq, 0, 0,
IRQ_GC_INIT_NESTED_LOCK);
if (ret)
goto err_generic;
/* peripheral interrupt chip */
gc = irq_get_domain_generic_chip(priv->domain, 0);
gc->unused = ~(BIT(priv->nr_perips) - 1);
gc->reg_base = priv->pdc_base;
/*
* IRQ_ROUTE contains wake bits, so we can't use the generic versions as
* they cache the mask
*/
gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE;
gc->chip_types[0].chip.irq_mask = perip_irq_mask;
gc->chip_types[0].chip.irq_unmask = perip_irq_unmask;
gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
/* syswake interrupt chip */
gc = irq_get_domain_generic_chip(priv->domain, 8);
gc->unused = ~(BIT(priv->nr_syswakes) - 1);
gc->reg_base = priv->pdc_base;
/* edge interrupts */
gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
gc->chip_types[0].handler = handle_edge_irq;
gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR;
gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.irq_set_type = syswake_irq_set_type;
gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
/* for standby we pass on to the shared syswake IRQ */
gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
/* level interrupts */
gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK;
gc->chip_types[1].handler = handle_level_irq;
gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR;
gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE;
gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[1].chip.irq_set_type = syswake_irq_set_type;
gc->chip_types[1].chip.irq_set_wake = pdc_irq_set_wake;
/* for standby we pass on to the shared syswake IRQ */
gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
/* Set up the hardware to enable interrupt routing */
pdc_intc_setup(priv);
/* Setup chained handlers for the peripheral IRQs */
for (i = 0; i < priv->nr_perips; ++i) {
irq = priv->perip_irqs[i];
irq_set_handler_data(irq, priv);
irq_set_chained_handler(irq, pdc_intc_perip_isr);
}
/* Setup chained handler for the syswake IRQ */
irq_set_handler_data(priv->syswake_irq, priv);
irq_set_chained_handler(priv->syswake_irq, pdc_intc_syswake_isr);
dev_info(&pdev->dev,
"PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n",
priv->nr_perips,
priv->nr_syswakes);
return 0;
err_generic:
irq_domain_remove(priv->domain);
return ret;
}
static int __init of_tb10x_init_irq(struct device_node *ictl,
struct device_node *parent)
{
int i, ret, nrirqs = of_irq_count(ictl);
struct resource mem;
struct irq_chip_generic *gc;
struct irq_domain *domain;
void __iomem *reg_base;
if (of_address_to_resource(ictl, 0, &mem)) {
pr_err("%s: No registers declared in DeviceTree.\n",
ictl->name);
return -EINVAL;
}
if (!request_mem_region(mem.start, resource_size(&mem),
ictl->name)) {
pr_err("%s: Request mem region failed.\n", ictl->name);
return -EBUSY;
}
reg_base = ioremap(mem.start, resource_size(&mem));
if (!reg_base) {
ret = -EBUSY;
pr_err("%s: ioremap failed.\n", ictl->name);
goto ioremap_fail;
}
domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
&irq_generic_chip_ops, NULL);
if (!domain) {
ret = -ENOMEM;
pr_err("%s: Could not register interrupt domain.\n",
ictl->name);
goto irq_domain_add_fail;
}
ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
2, ictl->name, handle_level_irq,
IRQ_NOREQUEST, IRQ_NOPROBE,
IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_err("%s: Could not allocate generic interrupt chip.\n",
ictl->name);
goto gc_alloc_fail;
}
gc = domain->gc->gc[0];
gc->reg_base = reg_base;
gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type;
gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE;
gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type;
gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS;
gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE;
gc->chip_types[1].handler = handle_edge_irq;
for (i = 0; i < nrirqs; i++) {
unsigned int irq = irq_of_parse_and_map(ictl, i);
irq_set_handler_data(irq, domain);
irq_set_chained_handler(irq, tb10x_irq_cascade);
}
ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
return 0;
gc_alloc_fail:
irq_domain_remove(domain);
irq_domain_add_fail:
iounmap(reg_base);
ioremap_fail:
release_mem_region(mem.start, resource_size(&mem));
return ret;
}
static int __init orion_bridge_irq_init(struct device_node *np,
struct device_node *parent)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct resource r;
struct irq_domain *domain;
struct irq_chip_generic *gc;
int ret, irq, nrirqs = 32;
/* get optional number of interrupts provided */
of_property_read_u32(np, "marvell,#interrupts", &nrirqs);
domain = irq_domain_add_linear(np, nrirqs,
&irq_generic_chip_ops, NULL);
if (!domain) {
pr_err("%s: unable to add irq domain\n", np->name);
return -ENOMEM;
}
ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_err("%s: unable to alloc irq domain gc\n", np->name);
return ret;
}
ret = of_address_to_resource(np, 0, &r);
if (ret) {
pr_err("%s: unable to get resource\n", np->name);
return ret;
}
if (!request_mem_region(r.start, resource_size(&r), np->name)) {
pr_err("%s: unable to request mem region\n", np->name);
return -ENOMEM;
}
/* Map the parent interrupt for the chained handler */
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0) {
pr_err("%s: unable to parse irq\n", np->name);
return -EINVAL;
}
gc = irq_get_domain_generic_chip(domain, 0);
gc->reg_base = ioremap(r.start, resource_size(&r));
if (!gc->reg_base) {
pr_err("%s: unable to map resource\n", np->name);
return -ENOMEM;
}
gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
/* mask and clear all interrupts */
writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
irq_set_handler_data(irq, domain);
irq_set_chained_handler(irq, orion_bridge_irq_handler);
return 0;
}
