void enable_usb_clocks(int index) { u32 cm_l3init_usb_otg_ss_clkctrl = 0; if (index == 0) { cm_l3init_usb_otg_ss_clkctrl = (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; /* Enable 960 MHz clock for dwc3 */ setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, OPTFCLKEN_REFCLK960M); /* Enable 32 KHz clock for USB_PHY1 */ setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); /* Enable 32 KHz clock for USB_PHY3 */ if (is_dra7xx()) setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); } else if (index == 1) { cm_l3init_usb_otg_ss_clkctrl = (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; /* Enable 960 MHz clock for dwc3 */ setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, OPTFCLKEN_REFCLK960M); /* Enable 32 KHz clock for dwc3 */ setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); /* Enable 60 MHz clock for USB2PHY2 */ setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); } u32 const clk_domains_usb[] = { 0 }; u32 const clk_modules_hw_auto_usb[] = { (*prcm)->cm_l3init_ocp2scp1_clkctrl, cm_l3init_usb_otg_ss_clkctrl, 0 }; u32 const clk_modules_explicit_en_usb[] = { 0 }; do_enable_clocks(clk_domains_usb, clk_modules_hw_auto_usb, clk_modules_explicit_en_usb, 1); }
/* DDR3 specific IO settings */ static void io_settings_ddr3(void) { u32 io_settings = 0; const struct ctrl_ioregs *ioregs; get_ioregs(&ioregs); writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); if (!is_dra7xx()) { writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); } /* omap5432 does not use lpddr2 */ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif1_sdram_config_ext); if (!is_dra72x()) writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif2_sdram_config_ext); if (is_omap54xx()) { /* Disable DLL select */ io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) & 0xFFEFFFFF); writel(io_settings, (*ctrl)->control_port_emif1_sdram_config); io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) & 0xFFEFFFFF); writel(io_settings, (*ctrl)->control_port_emif2_sdram_config); } else { writel(ioregs->ctrl_ddr_ctrl_ext_0, (*ctrl)->control_ddr_control_ext_0); } }
static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { const char **clk_names; u32 *clk_rates; int ret; if (!is_dra72x() && !is_dra7xx()) return; /* fixup DSP clocks */ clk_names = dra7_opp_dsp_clk_names; clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)]; ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM); if (ret) { printf("ft_fixup_clocks failed for DSP voltage domain: %s\n", fdt_strerror(ret)); return; } /* fixup IVA clocks */ clk_names = dra7_opp_iva_clk_names; clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)]; ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM); if (ret) { printf("ft_fixup_clocks failed for IVA voltage domain: %s\n", fdt_strerror(ret)); return; } /* fixup GPU clocks */ clk_names = dra7_opp_gpu_clk_names; clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)]; ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM); if (ret) { printf("ft_fixup_clocks failed for GPU voltage domain: %s\n", fdt_strerror(ret)); return; } }