static int __init soekris_init(void)
{
int i;
unsigned char *rombase, *bios;
if (!is_geode())
return 0;
rombase = ioremap(0xffff0000, 0xffff);
if (!rombase) {
printk(KERN_INFO "Soekris net5501 LED driver failed to get rombase");
return 0;
}
bios = rombase + 0x20; /* null terminated */
if (strncmp(bios, "comBIOS", 7))
goto unmap;
for (i = 0; i < ARRAY_SIZE(boards); i++) {
unsigned char *model = rombase + boards[i].offset;
if (strncmp(model, boards[i].sig, boards[i].len) == 0) {
printk(KERN_INFO "Soekris %s: %s\n", model, bios);
if (boards[i].init)
boards[i].init();
break;
}
}
unmap:
iounmap(rombase);
return 0;
}
static int __init cs553x_init(void)
{
int err = -ENXIO;
int i;
uint64_t val;
#ifdef CONFIG_MTD_PARTITIONS
int mtd_parts_nb = 0;
struct mtd_partition *mtd_parts = NULL;
#endif
/* If the CPU isn't a Geode GX or LX, abort */
if (!is_geode())
return -ENXIO;
/* If it doesn't have the CS553[56], abort */
rdmsrl(MSR_DIVIL_GLD_CAP, val);
val &= ~0xFFULL;
if (val != CAP_CS5535 && val != CAP_CS5536)
return -ENXIO;
/* If it doesn't have the NAND controller enabled, abort */
rdmsrl(MSR_DIVIL_BALL_OPTS, val);
if (val & PIN_OPT_IDE) {
printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
return -ENXIO;
}
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
}
/* Register all devices together here. This means we can easily hack it to
do mtdconcat etc. if we want to. */
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
if (cs553x_mtd[i]) {
/* If any devices registered, return success. Else the last error. */
#ifdef CONFIG_MTD_PARTITIONS
mtd_parts_nb = parse_mtd_partitions(cs553x_mtd[i], part_probes, &mtd_parts, 0);
if (mtd_parts_nb > 0) {
printk(KERN_NOTICE "Using command line partition definition\n");
add_mtd_partitions(cs553x_mtd[i], mtd_parts, mtd_parts_nb);
} else {
add_mtd_device(cs553x_mtd[i]);
}
#else
add_mtd_device(cs553x_mtd[i]);
#endif
err = 0;
}
}
return err;
}
static int __init net5501_init(void)
{
if (!is_geode())
return 0;
if (!net5501_present())
return 0;
register_net5501();
return 0;
}
static int __init geode_southbridge_init(void)
{
int timers;
if (!is_geode())
return -ENODEV;
init_lbars();
timers = geode_mfgpt_detect();
printk(KERN_INFO "geode: %d MFGPT timers available.\n", timers);
return 0;
}
static int __init olpc_init(void)
{
unsigned char *romsig;
/* The ioremap check is dangerous; limit what we run it on */
if (!is_geode() || cs5535_has_vsa2())
return 0;
spin_lock_init(&ec_lock);
romsig = ioremap(0xffffffc0, 16);
if (!romsig)
return 0;
if (strncmp(romsig, "CL1 Q", 7))
goto unmap;
if (strncmp(romsig+6, romsig+13, 3)) {
printk(KERN_INFO "OLPC BIOS signature looks invalid. "
"Assuming not OLPC\n");
goto unmap;
}
printk(KERN_INFO "OLPC board with OpenFirmware %.16s\n", romsig);
olpc_platform_info.flags |= OLPC_F_PRESENT;
/* get the platform revision */
platform_detect();
/* assume B1 and above models always have a DCON */
if (olpc_board_at_least(olpc_board(0xb1)))
olpc_platform_info.flags |= OLPC_F_DCON;
/* get the EC revision */
olpc_ec_cmd(EC_FIRMWARE_REV, NULL, 0,
(unsigned char *) &olpc_platform_info.ecver, 1);
#ifdef CONFIG_PCI_OLPC
/* If the VSA exists let it emulate PCI, if not emulate in kernel */
if (!cs5535_has_vsa2())
x86_init.pci.arch_init = pci_olpc_init;
#endif
printk(KERN_INFO "OLPC board revision %s%X (EC=%x)\n",
((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "",
olpc_platform_info.boardrev >> 4,
olpc_platform_info.ecver);
unmap:
iounmap(romsig);
return 0;
}
static int __init alix_init(void)
{
const char tinybios_sig[] = "PC Engines ALIX.";
const char coreboot_sig[] = "PC Engines\0ALIX.";
if (!is_geode())
return 0;
if (alix_present(0xf0000, tinybios_sig, sizeof(tinybios_sig) - 1) ||
alix_present(0x500, coreboot_sig, sizeof(coreboot_sig) - 1))
register_alix();
return 0;
}
static int __init alix_init(void)
{
const char tinybios_sig[] = "PC Engines ALIX.";
const char coreboot_sig[] = "PC Engines\0ALIX.";
if (!is_geode())
return 0;
if (alix_present(BIOS_SIGNATURE_TINYBIOS, tinybios_sig, sizeof(tinybios_sig) - 1) ||
alix_present(BIOS_SIGNATURE_COREBOOT, coreboot_sig, sizeof(coreboot_sig) - 1) ||
alix_present_dmi())
register_alix();
return 0;
}
static int __init cs553x_init(void)
{
int err = -ENXIO;
int i;
uint64_t val;
/* If the CPU isn't a Geode GX or LX, abort */
if (!is_geode())
return -ENXIO;
/* If it doesn't have the CS553[56], abort */
rdmsrl(MSR_DIVIL_GLD_CAP, val);
val &= ~0xFFULL;
if (val != CAP_CS5535 && val != CAP_CS5536)
return -ENXIO;
/* If it doesn't have the NAND controller enabled, abort */
rdmsrl(MSR_DIVIL_BALL_OPTS, val);
if (val & 1) {
printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
return -ENXIO;
}
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
}
/* Register all devices together here. This means we can easily hack it to
do mtdconcat etc. if we want to. */
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
if (cs553x_mtd[i]) {
add_mtd_device(cs553x_mtd[i]);
/* If any devices registered, return success. Else the last error. */
err = 0;
}
}
return err;
}
static int __init cs553x_init(void)
{
int err = -ENXIO;
int i;
uint64_t val;
if (!is_geode())
return -ENXIO;
rdmsrl(MSR_DIVIL_GLD_CAP, val);
val &= ~0xFFULL;
if (val != CAP_CS5535 && val != CAP_CS5536)
return -ENXIO;
rdmsrl(MSR_DIVIL_BALL_OPTS, val);
if (val & PIN_OPT_IDE) {
printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
return -ENXIO;
}
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
}
for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
if (cs553x_mtd[i]) {
mtd_device_parse_register(cs553x_mtd[i], NULL, NULL,
NULL, 0);
err = 0;
}
}
return err;
}