static int mm_pi_enable(struct pi *pi, int enable)
{
int ret;
pi_dbg(pi->id, PI_LOG_EN_DIS, "%s\n", __func__);
writel(0x00A5A501, KONA_ROOT_CLK_VA +
ROOT_CLK_MGR_REG_WR_ACCESS_OFFSET);
#ifdef CONFIG_PLL1_8PHASE_OFF_ERRATUM
if (is_pm_erratum(ERRATUM_PLL1_8PHASE_OFF)) {
if (enable && ref_8ph_en_pll1_clk)
clk_enable(ref_8ph_en_pll1_clk);
}
#endif
#ifdef CONFIG_MM_FREEZE_VAR500M_ERRATUM
if (is_pm_erratum(ERRATUM_MM_FREEZE_VAR500M) && enable)
var500m_clk_en_override(true);
#endif
ret = gen_pi_ops.enable(pi, enable);
#ifdef CONFIG_MM_FREEZE_VAR500M_ERRATUM
if (is_pm_erratum(ERRATUM_MM_FREEZE_VAR500M) && !enable)
var500m_clk_en_override(false);
#endif
#ifdef CONFIG_PLL1_8PHASE_OFF_ERRATUM
if (is_pm_erratum(ERRATUM_PLL1_8PHASE_OFF)) {
if (!enable && ref_8ph_en_pll1_clk)
clk_disable(ref_8ph_en_pll1_clk);
}
#endif
return ret;
}
int __init board_bcm59xx_init(void)
{
int ret = 0;
int irq;
bcmpmu_set_pullup_reg();
ret = gpio_request(PMU_DEVICE_INT_GPIO, "bcmpmu59xxx-irq");
if (ret < 0) {
printk(KERN_ERR "<%s> failed at gpio_request\n", __func__);
goto exit;
}
ret = gpio_direction_input(PMU_DEVICE_INT_GPIO);
if (ret < 0) {
printk(KERN_ERR "%s filed at gpio_direction_input.\n",
__func__);
goto exit;
}
irq = gpio_to_irq(PMU_DEVICE_INT_GPIO);
bcmpmu_i2c_pdata.irq = irq;
ret = i2c_register_board_info(PMU_DEVICE_I2C_BUSNO,
bcmpmu_i2c_info, ARRAY_SIZE(bcmpmu_i2c_info));
#if defined(CONFIG_SEC_CHARGING_FEATURE)
platform_add_devices(spa_devices, ARRAY_SIZE(spa_devices));
#endif
/* Workaround for VDDFIX leakage during deepsleep.
Will be fixed in Java A1 revision */
if (is_pm_erratum(ERRATUM_VDDFIX_LEAKAGE))
bcm59xxx_csr_data.constraints.initial_mode =
REGULATOR_MODE_IDLE;
return 0;
exit:
return ret;
}
static int __init __mm_pre_init_state(void)
{
if (is_pm_erratum(ERRATUM_PLL1_8PHASE_OFF)) {
if (ref_8ph_en_pll1_clk == NULL) {
ref_8ph_en_pll1_clk = clk_get(NULL,
REF_8PHASE_EN_PLL1_CLK_NAME_STR);
}
BUG_ON(IS_ERR_OR_NULL(ref_8ph_en_pll1_clk));
}
return 0;
}
static int mm_pi_enable(struct pi *pi, int enable)
{
int ret;
pi_dbg(pi->id, PI_LOG_EN_DIS, "%s\n", __func__);
#ifdef CONFIG_PLL1_8PHASE_OFF_ERRATUM
if (is_pm_erratum(ERRATUM_PLL1_8PHASE_OFF)) {
if (enable && ref_8ph_en_pll1_clk)
__clk_enable(ref_8ph_en_pll1_clk);
}
#endif
#ifdef CONFIG_MM_FREEZE_VAR500M_ERRATUM
if (is_pm_erratum(ERRATUM_MM_FREEZE_VAR500M) && enable)
mm_varvdd_clk_en_override(true);
#endif
ret = gen_pi_ops.enable(pi, enable);
#ifdef CONFIG_MM_FREEZE_VAR500M_ERRATUM
#ifdef CONFIG_MM_312M_SOURCE_CLK
if (is_pm_erratum(ERRATUM_MM_FREEZE_VAR500M) && enable)
mm_varvdd_clk_en_override(false);
#else
if (is_pm_erratum(ERRATUM_MM_FREEZE_VAR500M) && !enable)
mm_varvdd_clk_en_override(false);
#endif
#endif
#ifdef CONFIG_PLL1_8PHASE_OFF_ERRATUM
#ifdef CONFIG_MOVE_MM_CLK_TO_PLL0
if (is_pm_erratum(ERRATUM_PLL1_8PHASE_OFF)) {
if (enable && ref_8ph_en_pll1_clk)
__clk_disable(ref_8ph_en_pll1_clk);
}
#else
if (is_pm_erratum(ERRATUM_PLL1_8PHASE_OFF)) {
if (!enable && ref_8ph_en_pll1_clk)
__clk_disable(ref_8ph_en_pll1_clk);
}
#endif
#endif
return ret;
}
int __init rgltr_init(void)
{
int i, j, k, int_val;
struct device_node *np;
struct property *prop;
const char *output[15], *val;
size_t total = 0, len = 0;
np = of_find_matching_node(NULL, bcmpmu_regulator_dt_ids);
if (!np) {
pr_err("device tree support for rgltr not found\n");
return 0;
}
for (i = 0; i < BCMPMU_REGULATOR_MAX; i++) {
prop = of_find_property(np,
rgltr_pdata.bcmpmu_rgltr[i].name, NULL);
if (prop) {
val = prop->value;
for (j = 0, total = 0, len = 0; total < prop->length;
len = strlen(val) + 1, total += len,
val += len, j++)
output[j] = val;
/* coverity[secure_coding] */
sscanf(output[0], "%d", &int_val);
rgltr_pdata.bcmpmu_rgltr[i].initdata->
num_consumer_supplies = int_val;
rgltr_pdata.bcmpmu_rgltr[i].initdata->
consumer_supplies = kzalloc(sizeof(struct
regulator_consumer_supply)*int_val,
GFP_KERNEL);
for (j = 0, k = 1; j < int_val; j++, k++)
rgltr_pdata.bcmpmu_rgltr[i].initdata->
consumer_supplies[j].supply = output[k];
/* coverity[secure_coding] */
sscanf(output[k++], "%d", &int_val);
rgltr_pdata.bcmpmu_rgltr[i].initdata->
constraints.always_on = int_val;
/* coverity[secure_coding] */
sscanf(output[k++], "%d", &int_val);
rgltr_pdata.bcmpmu_rgltr[i].pc_pins_map = int_val;
/* coverity[secure_coding] */
sscanf(output[k++], "%d", &int_val);
rgltr_pdata.bcmpmu_rgltr[i].initdata->constraints.
initial_mode = int_val;
/* coverity[secure_coding] */
sscanf(output[k++], "%d", &int_val);
rgltr_pdata.bcmpmu_rgltr[i].initdata->constraints.
boot_on = int_val;
/* coverity[secure_coding] */
sscanf(output[k++], "%d", &int_val);
rgltr_pdata.bcmpmu_rgltr[i].req_volt = int_val;
}
}
/* Workaround for VDDFIX leakage during deepsleep.
Will be fixed in Java A1 revision */
if (is_pm_erratum(ERRATUM_VDDFIX_LEAKAGE))
bcm59xxx_csr_data.constraints.initial_mode =
REGULATOR_MODE_IDLE;
return 0;
}
