static int pc98_serial_initfn(ISADevice *dev)
{
SerialPortState *s = DO_UPCAST(SerialPortState, dev, dev);
isa_init_irq(dev, &s->pic, s->irq);
register_ioport_write(0x30, 1, 1, sio_data_write, s);
register_ioport_read(0x30, 1, 1, sio_data_read, s);
isa_init_ioport(dev, 0x30);
register_ioport_write(0x32, 1, 1, sio_cmd_write, s);
register_ioport_read(0x32, 1, 1, sio_status_read, s);
isa_init_ioport(dev, 0x32);
s->sio_timer = qemu_new_timer(rt_clock, sio_timer_handler, s);
pc98_serial_reset(s);
qemu_register_reset(pc98_serial_reset, s);
return 0;
}
static int pc98_kbd_initfn(ISADevice *dev)
{
KeyBoardState *s = DO_UPCAST(KeyBoardState, dev, dev);
isa_init_irq(dev, &s->pic, s->irq);
register_ioport_write(0x41, 1, 1, sio_data_write, s);
register_ioport_read(0x41, 1, 1, sio_data_read, s);
isa_init_ioport(dev, 0x41);
register_ioport_write(0x43, 1, 1, sio_cmd_write, s);
register_ioport_read(0x43, 1, 1, sio_status_read, s);
isa_init_ioport(dev, 0x43);
s->sio_timer = qemu_new_timer(rt_clock, sio_timer_handler, s);
qemu_add_kbd_event_handler(kbd_event_handler, s);
pc98_kbd_reset(s);
qemu_register_reset(pc98_kbd_reset, s);
return 0;
}
static int parallel_isa_initfn(ISADevice *dev)
{
static int index;
ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
ParallelState *s = &isa->state;
int base;
uint8_t dummy;
if (!s->chr) {
fprintf(stderr, "Can't create parallel device, empty char device\n");
exit(1);
}
if (isa->index == -1)
isa->index = index;
if (isa->index >= MAX_PARALLEL_PORTS)
return -1;
if (isa->iobase == -1)
isa->iobase = isa_parallel_io[isa->index];
index++;
base = isa->iobase;
isa_init_irq(dev, &s->irq, isa->isairq);
qemu_register_reset(parallel_reset, s);
if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
s->status = dummy;
}
if (s->hw_driver) {
register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
isa_init_ioport_range(dev, base, 8);
register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
isa_init_ioport(dev, base+4);
register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
isa_init_ioport_range(dev, base+0x400, 8);
}
else {
register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
isa_init_ioport_range(dev, base, 8);
}
return 0;
}
void isa_register_portio_list(ISADevice *dev, uint16_t start,
const MemoryRegionPortio *pio_start,
void *opaque, const char *name)
{
PortioList *piolist = g_new(PortioList, 1);
/* START is how we should treat DEV, regardless of the actual
contents of the portio array. This is how the old code
actually handled e.g. the FDC device. */
isa_init_ioport(dev, start);
portio_list_init(piolist, OBJECT(dev), pio_start, opaque, name);
portio_list_add(piolist, isabus->address_space_io, start);
}
void isa_register_portio_list(ISADevice *dev, uint16_t start,
const MemoryRegionPortio *pio_start,
void *opaque, const char *name)
{
PortioList piolist;
/* START is how we should treat DEV, regardless of the actual
contents of the portio array. This is how the old code
actually handled e.g. the FDC device. */
isa_init_ioport(dev, start);
/* FIXME: the device should store created PortioList in its state. Note
that DEV can be NULL here and that single device can register several
portio lists. Current implementation is leaking memory allocated
in portio_list_init. The leak is not critical because it happens only
at initialization time. */
portio_list_init(&piolist, OBJECT(dev), pio_start, opaque, name);
portio_list_add(&piolist, isabus->address_space_io, start);
}
static int pc98_ide_initfn(ISADevice *dev)
{
PC98IDEState *s = DO_UPCAST(PC98IDEState, dev, dev);
int i;
ide_bus_new(&s->bus[0], &s->dev.qdev, 0);
ide_bus_new(&s->bus[1], &s->dev.qdev, 1);
isa_init_irq(dev, &s->irq, s->isairq);
ide_init2(&s->bus[0], s->irq);
ide_init2(&s->bus[1], s->irq);
register_ioport_write(0xf0, 1, 1, pc98_ide_cpu_shutdown, s);
register_ioport_read(0xf0, 1, 1, pc98_ide_connection_read, s);
isa_init_ioport(dev, 0xf0);
register_ioport_write(0x430, 1, 1, pc98_ide_bank_write, s);
register_ioport_read(0x430, 1, 1, pc98_ide_bank_read, s);
isa_init_ioport(dev, 0x430);
register_ioport_write(0x432, 1, 1, pc98_ide_bank_write, s);
register_ioport_read(0x432, 1, 1, pc98_ide_bank_read, s);
isa_init_ioport(dev, 0x432);
for (i = 0; i < 8; i++) {
register_ioport_write(0x640 + (i << 1), 1, 1, pc98_ide_ioport_write, s);
register_ioport_read(0x640 + (i << 1), 1, 1, pc98_ide_ioport_read, s);
isa_init_ioport(dev, 0x640 + (i << 1));
}
register_ioport_write(0x640, 2, 2, pc98_ide_data_writew, s);
register_ioport_read(0x640, 2, 2, pc98_ide_data_readw, s);
/*isa_init_ioport_range(dev, 0x640, 2);*/
register_ioport_write(0x640, 4, 4, pc98_ide_data_writel, s);
register_ioport_read(0x640, 4, 4, pc98_ide_data_readl, s);
/*isa_init_ioport_range(dev, 0x640, 4);*/
register_ioport_write(0x74c, 1, 1, pc98_ide_digital_write, s);
register_ioport_read(0x74c, 1, 1, pc98_ide_status_read, s);
isa_init_ioport(dev, 0x74c);
register_ioport_read(0x74e, 1, 1, pc98_ide_digital_read, s);
isa_init_ioport(dev, 0x74e);
vmstate_register(&dev->qdev, 0, &vmstate_ide_pc98, s);
pc98_ide_reset(&dev->qdev);
return 0;
};
void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start)
{
memory_region_add_subregion(isabus->address_space_io, start, io);
isa_init_ioport(dev, start);
}