int iwm_send_ct_kill_cfg(struct iwm_priv *iwm, u8 entry, u8 exit)
{
struct iwm_ct_kill_cfg_cmd cmd;
cmd.entry_threshold = entry;
cmd.exit_threshold = exit;
return iwm_send_lmac_ptrough_cmd(iwm, REPLY_CT_KILL_CONFIG_CMD, &cmd,
sizeof(struct iwm_ct_kill_cfg_cmd), 0);
}
int iwm_send_prio_table(struct iwm_priv *iwm)
{
struct iwm_coex_prio_table_cmd coex_table_cmd;
u32 coex_enabled, mode_enabled;
memset(&coex_table_cmd, 0, sizeof(struct iwm_coex_prio_table_cmd));
coex_table_cmd.flags = COEX_FLAGS_STA_TABLE_VALID_MSK;
switch (iwm->conf.coexist_mode) {
case COEX_MODE_XOR:
case COEX_MODE_CM:
coex_enabled = 1;
break;
default:
coex_enabled = 0;
break;
}
switch (iwm->conf.mode) {
case UMAC_MODE_BSS:
case UMAC_MODE_IBSS:
mode_enabled = 1;
break;
default:
mode_enabled = 0;
break;
}
if (coex_enabled && mode_enabled) {
coex_table_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK |
COEX_FLAGS_ASSOC_WAKEUP_UMASK_MSK |
COEX_FLAGS_UNASSOC_WAKEUP_UMASK_MSK;
switch (iwm->conf.coexist_mode) {
case COEX_MODE_XOR:
memcpy(coex_table_cmd.sta_prio, iwm_sta_xor_prio_tbl,
sizeof(iwm_sta_xor_prio_tbl));
break;
case COEX_MODE_CM:
memcpy(coex_table_cmd.sta_prio, iwm_sta_cm_prio_tbl,
sizeof(iwm_sta_cm_prio_tbl));
break;
default:
IWM_ERR(iwm, "Invalid coex_mode 0x%x\n",
iwm->conf.coexist_mode);
break;
}
} else
IWM_WARN(iwm, "coexistense disabled\n");
return iwm_send_lmac_ptrough_cmd(iwm, COEX_PRIORITY_TABLE_CMD,
&coex_table_cmd,
sizeof(struct iwm_coex_prio_table_cmd), 1);
}
int iwm_send_periodic_calib_cfg(struct iwm_priv *iwm, u8 calib_requested)
{
struct iwm_lmac_cal_cfg_cmd cal_cfg_cmd;
memset(&cal_cfg_cmd, 0, sizeof(struct iwm_lmac_cal_cfg_cmd));
cal_cfg_cmd.ucode_cfg.periodic.enable = cpu_to_le32(calib_requested);
cal_cfg_cmd.ucode_cfg.periodic.start = cpu_to_le32(calib_requested);
return iwm_send_lmac_ptrough_cmd(iwm, CALIBRATION_CFG_CMD, &cal_cfg_cmd,
sizeof(struct iwm_lmac_cal_cfg_cmd), 0);
}
int iwm_send_init_calib_cfg(struct iwm_priv *iwm, u8 calib_requested)
{
struct iwm_lmac_cal_cfg_cmd cal_cfg_cmd;
memset(&cal_cfg_cmd, 0, sizeof(struct iwm_lmac_cal_cfg_cmd));
cal_cfg_cmd.ucode_cfg.init.enable = cpu_to_le32(calib_requested);
cal_cfg_cmd.ucode_cfg.init.start = cpu_to_le32(calib_requested);
cal_cfg_cmd.ucode_cfg.init.send_res = cpu_to_le32(calib_requested);
cal_cfg_cmd.ucode_cfg.flags =
cpu_to_le32(CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_AFTER_MSK);
return iwm_send_lmac_ptrough_cmd(iwm, CALIBRATION_CFG_CMD, &cal_cfg_cmd,
sizeof(struct iwm_lmac_cal_cfg_cmd), 1);
}
int iwm_send_calib_results(struct iwm_priv *iwm)
{
int i, ret = 0;
for (i = PHY_CALIBRATE_OPCODES_NUM; i < CALIBRATION_CMD_NUM; i++) {
if (test_bit(i - PHY_CALIBRATE_OPCODES_NUM,
&iwm->calib_done_map)) {
IWM_DBG_CMD(iwm, DBG,
"Send calibration %d result\n", i);
ret |= iwm_send_lmac_ptrough_cmd(iwm,
REPLY_PHY_CALIBRATION_CMD,
iwm->calib_res[i].buf,
iwm->calib_res[i].size, 0);
kfree(iwm->calib_res[i].buf);
iwm->calib_res[i].buf = NULL;
iwm->calib_res[i].size = 0;
}
}
return ret;
}
