static inline void do_reset(void) { #if 1 /* Resetting PCI bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); }
static void jmr3927_machine_restart(char *command) { local_irq_disable(); #if 1 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); (*_machine_halt)(); }
static void jmr3927_machine_restart(char *command) { local_irq_disable(); #if 1 /* Resetting PCI bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); /* fallback */ (*_machine_halt)(); }
static inline void do_reset(void) { #ifdef CONFIG_TC35815 extern void tc35815_killall(void); tc35815_killall(); #endif #if 1 /* Resetting PCI bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); }
static void jmr3927_board_init() { char *argptr; #ifdef CONFIG_PCI mips_pci_io_base = JMR3927_PCIIO; mips_pci_io_size = JMR3927_PCIIO_SIZE; mips_pci_mem_base = JMR3927_PCIMEM; mips_pci_mem_size = JMR3927_PCIMEM_SIZE; #endif tx3927_setup(); #ifdef CONFIG_VT conswitchp = &dummy_con; #endif if (jmr3927_have_isac()) { #ifdef CONFIG_FB_E1355 argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "video=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " video=e1355fb:crt16h"); } #endif #ifdef CONFIG_BLK_DEV_IDE /* overrides PCI-IDE */ #endif #ifdef CONFIG_PC_KEYB //not yet kbd_ops = &jmr3927_kbd_ops; #endif } #ifdef USE_RTC_DS1742 if (jmr3927_have_nvram()) { rtc_ops = &jmr3927_rtc_ops; } #endif /* SIO0 DTR on */ jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); jmr3927_led_set(0); if (jmr3927_have_isac()) jmr3927_io_led_set(0); printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_dipsw1(), jmr3927_dipsw2(), jmr3927_dipsw3(), jmr3927_dipsw4()); if (jmr3927_have_isac()) printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n", jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_io_dipsw()); }
static void __init jmr3927_pci_setup(void) { #ifdef CONFIG_PCI int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB); struct pci_controller *c; c = txx9_alloc_pci_controller(&txx9_primary_pcic, JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE, JMR3927_PCIIO, JMR3927_PCIIO_SIZE); register_pci_controller(c); if (!extarb) { jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); } tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb); tx3927_setup_pcierr_irq(); #endif }
static void __init jmr3927_board_init(void) { tx3927_setup(); /* SIO0 DTR on */ jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); jmr3927_led_set(0); printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_dipsw1(), jmr3927_dipsw2(), jmr3927_dipsw3(), jmr3927_dipsw4()); }
static void __init jmr3927_board_init(void) { txx9_cpu_clock = JMR3927_CORECLK; tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; tx3927_ccfgptr->pcfg |= TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); tx3927_setup(); __raw_writel(0x0000f000, &tx3927_pioptr->dir); gpio_request(11, "dipsw1"); gpio_request(10, "dipsw2"); jmr3927_pci_setup(); jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); jmr3927_led_set(0); printk(KERN_INFO "JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_dipsw1(), jmr3927_dipsw2(), jmr3927_dipsw3(), jmr3927_dipsw4()); }
void __init tx3927_setup(void) { int i; /* SDRAMC are configured by PROM */ /* ROMC */ tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; /* CCFG */ /* enable Timeout BusError */ if (jmr3927_ccfg_toeon) tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; /* clear BusErrorOnWrite flag */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; /* Disable PCI snoop */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; #ifdef DO_WRITE_THROUGH /* Enable PCI SNOOP - with write through only */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; #endif /* Pin selection */ tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; tx3927_ccfgptr->pcfg |= TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); /* IRC */ /* disable interrupt control */ tx3927_ircptr->cer = 0; /* mask all IRC interrupts */ tx3927_ircptr->imr = 0; for (i = 0; i < TX3927_NUM_IR / 2; i++) { tx3927_ircptr->ilr[i] = 0; } /* setup IRC interrupt mode (Low Active) */ for (i = 0; i < TX3927_NUM_IR / 8; i++) { tx3927_ircptr->cr[i] = 0; } /* TMR */ /* disable all timers */ for (i = 0; i < TX3927_NR_TMR; i++) { tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE; tx3927_tmrptr(i)->tisr = 0; tx3927_tmrptr(i)->cpra = 0xffffffff; tx3927_tmrptr(i)->itmr = 0; tx3927_tmrptr(i)->ccdr = 0; tx3927_tmrptr(i)->pgmr = 0; } /* DMA */ tx3927_dmaptr->mcr = 0; for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) { /* reset channel */ tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; tx3927_dmaptr->ch[i].ccr = 0; } /* enable DMA */ #ifdef __BIG_ENDIAN tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; #else tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif #ifdef CONFIG_PCI /* PCIC */ printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", tx3927_pcicptr->did, tx3927_pcicptr->vid, tx3927_pcicptr->rid); if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { printk("External\n"); /* XXX */ } else { printk("Internal\n"); /* Reset PCI Bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); /* Disable External PCI Config. Access */ tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; #ifdef __BIG_ENDIAN tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | TX3927_PCIC_LBC_TIBSE | TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; #endif /* LB->PCI mappings */ tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); tx3927_pcicptr->ilbioma = mips_pci_io_base; tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->ilbmma = mips_pci_mem_base; tx3927_pcicptr->ipbmma = mips_pci_mem_base; /* PCI->LB mappings */ tx3927_pcicptr->iobas = 0xffffffff; tx3927_pcicptr->ioba = 0; tx3927_pcicptr->tlbioma = 0; tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->mba = 0; tx3927_pcicptr->tlbmma = 0; #ifndef JMR3927_INIT_INDIRECT_PCI /* Enable Direct mapping Address Space Decoder */ tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; #endif /* Clear All Local Bus Status */ tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; /* Enable All Local Bus Interrupts */ tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; /* Clear All PCI Status Error */ tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; /* Enable All PCI Status Error Interrupts */ tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; /* PCIC Int => IRC IRQ10 */ tx3927_pcicptr->il = TX3927_IR_PCI; #if 1 /* Target Control (per errata) */ tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; #endif /* Enable Bus Arbiter */ #if 0 tx3927_pcicptr->req_trace = 0x73737373; #endif tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | #if 1 PCI_COMMAND_IO | #endif PCI_COMMAND_PARITY | PCI_COMMAND_SERR; } #endif /* CONFIG_PCI */ /* PIO */ /* PIO[15:12] connected to LEDs */ tx3927_pioptr->dir = 0x0000f000; tx3927_pioptr->maskcpu = 0; tx3927_pioptr->maskext = 0; { unsigned int conf; conf = read_c0_conf(); if (!(conf & TX39_CONF_ICE)) printk("TX3927 I-Cache disabled.\n"); if (!(conf & TX39_CONF_DCE)) printk("TX3927 D-Cache disabled.\n"); else if (!(conf & TX39_CONF_WBON)) printk("TX3927 D-Cache WriteThrough.\n"); else if (!(conf & TX39_CONF_CWFON)) printk("TX3927 D-Cache WriteBack.\n"); else printk("TX3927 D-Cache WriteBack (CWF) .\n"); } }
static void __init tx3927_setup(void) { int i; #ifdef CONFIG_PCI unsigned long mips_pci_io_base = JMR3927_PCIIO; unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; unsigned long mips_pci_mem_base = JMR3927_PCIMEM; unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ unsigned long mips_pci_io_pciaddr = 0; #endif /* SDRAMC are configured by PROM */ /* ROMC */ tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; /* CCFG */ /* enable Timeout BusError */ if (jmr3927_ccfg_toeon) tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; /* clear BusErrorOnWrite flag */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; /* Disable PCI snoop */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; /* do reset on watchdog */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; #ifdef DO_WRITE_THROUGH /* Enable PCI SNOOP - with write through only */ tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; #endif /* Pin selection */ tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; tx3927_ccfgptr->pcfg |= TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); /* TMR */ for (i = 0; i < TX3927_NR_TMR; i++) txx9_tmr_init(TX3927_TMR_REG(i)); /* DMA */ tx3927_dmaptr->mcr = 0; for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { /* reset channel */ tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; tx3927_dmaptr->ch[i].ccr = 0; } /* enable DMA */ #ifdef __BIG_ENDIAN tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; #else tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif #ifdef CONFIG_PCI /* PCIC */ printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", tx3927_pcicptr->did, tx3927_pcicptr->vid, tx3927_pcicptr->rid); if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { printk("External\n"); /* XXX */ } else { printk("Internal\n"); /* Reset PCI Bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); udelay(100); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); /* Disable External PCI Config. Access */ tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; #ifdef __BIG_ENDIAN tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | TX3927_PCIC_LBC_TIBSE | TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; #endif /* LB->PCI mappings */ tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); tx3927_pcicptr->ilbioma = mips_pci_io_base; tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->ilbmma = mips_pci_mem_base; tx3927_pcicptr->ipbmma = mips_pci_mem_base; /* PCI->LB mappings */ tx3927_pcicptr->iobas = 0xffffffff; tx3927_pcicptr->ioba = 0; tx3927_pcicptr->tlbioma = 0; tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); tx3927_pcicptr->mba = 0; tx3927_pcicptr->tlbmma = 0; /* Enable Direct mapping Address Space Decoder */ tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; /* Clear All Local Bus Status */ tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; /* Enable All Local Bus Interrupts */ tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; /* Clear All PCI Status Error */ tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; /* Enable All PCI Status Error Interrupts */ tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; /* PCIC Int => IRC IRQ10 */ tx3927_pcicptr->il = TX3927_IR_PCI; /* Target Control (per errata) */ tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; /* Enable Bus Arbiter */ tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; } #endif /* CONFIG_PCI */ /* PIO */ /* PIO[15:12] connected to LEDs */ __raw_writel(0x0000f000, &tx3927_pioptr->dir); __raw_writel(0, &tx3927_pioptr->maskcpu); __raw_writel(0, &tx3927_pioptr->maskext); txx9_gpio_init(TX3927_PIO_REG, 0, 16); gpio_request(11, "dipsw1"); gpio_request(10, "dipsw2"); { unsigned int conf; conf = read_c0_conf(); if (!(conf & TX39_CONF_ICE)) printk("TX3927 I-Cache disabled.\n"); if (!(conf & TX39_CONF_DCE)) printk("TX3927 D-Cache disabled.\n"); else if (!(conf & TX39_CONF_WBON)) printk("TX3927 D-Cache WriteThrough.\n"); else if (!(conf & TX39_CONF_CWFON)) printk("TX3927 D-Cache WriteBack.\n"); else printk("TX3927 D-Cache WriteBack (CWF) .\n"); } }