示例#1
0
int board_early_init_f(void)
{
	init_plls();

	k2g_mux_config();

	k2g_reset_mux_config();

	/* deassert FLASH_HOLD */
	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
		     BIT(9));
	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
		     BIT(9));

	return 0;
}
示例#2
0
int embedded_dtb_select(void)
{
	int rc;
	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
			CONFIG_EEPROM_CHIP_ADDRESS);
	if (rc) {
		rc = k2g_alt_board_detect();
		if (rc) {
			printf("Unable to do board detection\n");
			return -1;
		}
	}

	fdtdec_setup();

	k2g_mux_config();

	k2g_reset_mux_config();

	if (board_is_k2g_gp() || board_is_k2g_g1()) {
		/* deassert FLASH_HOLD */
		clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
			     BIT(9));
		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
			     BIT(9));
	} else if (board_is_k2g_ice()) {
		/* GBE Phy workaround. For Phy to latch the input
		 * configuration, a GPIO reset is asserted at the
		 * Phy reset pin to latch configuration correctly after SoC
		 * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
		 * board. Just do a low to high transition.
		 */
		clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
			     BIT(10));
		setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
			     BIT(10));
		/* Delay just to get a transition to high */
		udelay(100);
		setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
			     BIT(10));
	}

	return 0;
}
示例#3
0
int board_early_init_f(void)
{
	init_plls();

	k2g_mux_config();

	k2g_reset_mux_config();

	/* deassert FLASH_HOLD */
	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
		     BIT(9));
	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
		     BIT(9));

	if (psc_enable_module(KS2_LPSC_GPMC))
		printf("%s can't enable gpmc\n", __func__);

	return 0;
}