void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
console_init();
enable_rom_decode();
printk(BIOS_INFO, "now booting... \n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
setup_default_resource_map();
setup_coherent_ht_domain();
wait_all_core0_started();
printk(BIOS_INFO, "now booting... All core 0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
init_timer();
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
print_debug_hex8(needs_reset);
needs_reset |= optimize_link_incoherent_ht(sysinfo);
print_debug_hex8(needs_reset);
needs_reset |= k8t890_early_setup_ht();
print_debug_hex8(needs_reset);
vt8237_early_network_init(NULL);
vt8237_early_spi_init();
if (needs_reset) {
printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
printk(BIOS_DEBUG, "FAILED!\n");
}
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
/* allow LDT STOP asserts */
vt8237_sb_enable_fid_vid();
enable_fid_change();
print_debug("after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
/* Stop the APs so we can start them later in init. */
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
DIMM0, DIMM2, 0, 0,
0, 0, 0, 0,
// Node 1
DIMM1, DIMM3, 0, 0,
0, 0, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_rom_decode();
print_info("now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
}
// FIXME why is this executed again? --->
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_rom_decode();
// <--- FIXME why is this executed again?
print_info("now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
setup_default_resource_map();
setup_coherent_ht_domain();
wait_all_core0_started();
print_info("now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
init_timer();
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
print_debug("ht reset -\n");
soft_reset();
}
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
enable_fid_change();
init_fidvid_bsp(bsp_apicid);
/* Stop the APs so we can start them later in init. */
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
DIMM0, DIMM1, DIMM2, 0,
0, 0, 0, 0,
// Node 1
0, 0, 0, 0,
0, 0, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_rom_decode();
print_info("now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
}
print_info("now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
setup_default_resource_map();
setup_coherent_ht_domain();
wait_all_core0_started();
print_info("now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
init_timer();
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
print_debug("ht reset -\n");
soft_reset();
}
/* the HT settings needs to be OK, because link freq change may cause HT disconnect */
vt8237_sb_enable_fid_vid();
enable_fid_change();
init_fidvid_bsp(bsp_apicid);
/* Stop the APs so we can start them later in init. */
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* this seems to be some GPIO on the SMBus--in any case, setting these
* two bits reduces the pullup impedance of the bus lines and is required
* in order to be able to read SPD info */
smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
unsigned char mask;
mask = 0;
// mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */
// mask |= 2 /* V-Link voltage 2.6 V (not verified either) */
smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2)));
smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask));
mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */
mask = 3 - (mask - 25);
smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4));
smbus_write_byte(0x4a, 0x03, 0x04 | mask);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}