void L1Audio_LSetEvent( uint16 audio_id, void *data )
{
uint32 savedMask;
savedMask = SaveAndSetIRQMask();
l1audio.evData[audio_id] = data;
l1audio.event_flag |= (1 << audio_id);
RestoreIRQMask( savedMask );
kal_activate_hisr( l1audio.hisr ); /* Activate L1Audio HISR */
}
/*-----------------------------------------------------------------------*
*
* GPT 1us LISR function,
* pass to gpt_hw layer as a function pointer
*
*------------------------------------------------------------------------*/
void GPT_DEBUG_Lisr(kal_uint32 vector)
{
/*ASSERT( (MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER) == vector) || \
(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER) == vector) );*/
#if defined(MT6290) && defined(__ARM7EJ_S__)
IRQClearInt(vector);
#endif /* end of "defined(MT6290) && defined(__ARM7EJ_S__)" */
#if defined (__MTK_TARGET__) && !defined(__GPTDEBUG_HISR_DISABLE__) && defined(__LTE_RAT__)
kal_activate_hisr(gpt_debug_hisr);
#endif
}
void L1Audio_TrigD2CHisr(uint16 magicNo)
{
int32 I;
for (I = 0; I < MAX_HISR_HANDLER; I++)
{
if (magicNo == l1audio.hisrMagicNo[I])
{
l1audio.hisrMagicFlag |= (1<<I);
kal_activate_hisr(l1audio.hisr);
return;
}
}
}
void cc_irq_lisr(kal_uint32 irqid)
{
kal_uint32 index;
/* remap irqid from line to code */
extern kal_uint8 irqLine[];
irqid = irqLine[irqid];
index = irqid - CC_IRQ_INTR_ID_START;
if (cc_irq_cb_in_hisr[index] == KAL_TRUE)
{
ASSERT(cc_irq_is_triggered[index] == KAL_FALSE);
cc_irq_is_triggered[index] = KAL_TRUE;
kal_activate_hisr(cc_irq_hisrid);
cc_irq_mask(index);
}
else
{
cc_irq_isr(index);
}
}
/*************************************************************************
* FUNCTION
* isrC_Main
*
* DESCRIPTION
* This function implement IRQ's LISR main dispatch routine
*
* CALLS
*
* CALL BY
* INT_IRQ_Parse()
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
#if !defined(__SSDVT_TEST__)
#if defined(MT6290) && defined(__ARM7EJ_S__)
void DEVDRV_LS_COPRO_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx)
#else /* defined(MT6290) && defined(__ARM7EJ_S__) */
void DEVDRV_LS_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx)
#endif /* else of "defined(MT6290) && defined(__ARM7EJ_S__)" */
{
#if defined(__UNIFIED_ISR_LEVEL__)
// kal_hisr processing_ehisrid;
kal_hisrid processing_hisrid;
#else /* __UNIFIED_ISR_LEVEL__ */
void *processing_lisr_backup;
kal_uint16 processing_irqx_backup;
processing_lisr_backup = processing_lisr;
processing_irqx_backup = processing_irqx;
#endif /* __UNIFIED_ISR_LEVEL__ */
processing_irqx = irqx;
processing_lisr = (void*)lisr_dispatch_tbl[irqx].lisr_handler;
processing_irqCnt++;
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
CPU_SET_CONTEXT_ID(0xaaaa0000 | ((kal_uint32)processing_irqx));
#ifdef __SWDBG_SUPPORT__
*SWDBG_MPCON = ((irqx + 0x100) << 16) | 0x8000;
#endif /* __SWDBG_SUPPORT__ */
#ifdef __WAKEUP_IRQ_DEBUG__
if (wkup_intr_log_indx != WKUP_LOG_BUF_MAX) {
wkup_intr_log_buf[wkup_intr_log_indx].irq = processing_irqx;
wkup_intr_log_indx++;
if (wkup_intr_log_indx == WKUP_LOG_BUF_MAX) {
wkup_intr_log_indx = 0;
}
}
if (wkup_timer_log_indx != WKUP_LOG_BUF_MAX) {
if (wake_tm_name != NULL) {
wkup_timer_log_buf[wkup_timer_log_indx].timer_name = wake_tm_name;
wake_tm_name = NULL;
wkup_timer_log_indx++;
if (wkup_timer_log_indx == WKUP_LOG_BUF_MAX) {
wkup_timer_log_indx = 0;
}
}
}
#endif /* __WAKEUP_IRQ_DEBUG__ */
#if defined(DEBUG_KAL) && defined(DEBUG_TIMER) && defined(__CR4__)
if(TimerHISR_State == 1)
{
GET_CURRENT_TIME(TimerHISR_Exclude_Start_Time);
TimerHISR_State = 2;
}
#endif
#if defined(__TP_SUPPORT_TIMING_CHECK__)
if(Thread_Protect_State==1)
{
Thread_Protect_State=2;
TP_Exclude_Start_Time = ust_get_current_time();
}
#endif
#ifdef __DEMAND_PAGING_PERFORMANCE_PROFILING__
demp_preempt_time_start();
#endif
#if defined(__UNIFIED_ISR_LEVEL__)
// processing_ehisrid = intrID2hisrEID[irqx];
// ASSERT(0xFF != processing_ehisrid);
// processing_hisrid = hisrid_g[processing_ehisrid];
processing_hisrid = intrID2hisrID[irqx];
if(processing_hisrid != drv_hisr)
{
EXT_ASSERT(NULL != processing_hisrid, irqx, processing_irqCnt, (kal_uint32)processing_lisr);
kal_activate_hisr(processing_hisrid);
}
else
{
drv_active_hisr(irqx);
}
/* no nested interrupt */
processing_lisr = NULL;
processing_irqx = IRQ_NOT_LISR_CONTEXT;
#else /* __UNIFIED_ISR_LEVEL__ */
ReEnableIRQ();
#if defined(__CR4__)
IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_enter_time[irqx]));
#elif defined(__MTK_MMU_V2__)
IFDEF_LISR_MEASURE_TIME(lisr_enter_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
#endif
lisr_dispatch_tbl[irqx].lisr_handler(irqx);
#if defined(__CR4__)
IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_leave_time[irqx]));
#elif defined(__MTK_MMU_V2__)
IFDEF_LISR_MEASURE_TIME(lisr_leave_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
#endif
DisableIRQ();
processing_irqx = processing_irqx_backup;
processing_lisr = processing_lisr_backup;
#endif /* __UNIFIED_ISR_LEVEL__ */
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_END_CSM(0xaaaaaaaa);
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaaaaaa);
}
CPU_SET_CONTEXT_ID(0xaaaaaaaa);
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
/* Binary-coded IRQ idx */
SYS_endIsr((kal_uint8)irqx);
}
void L1SP_D2C_LISR( uint16 itype )
{
l1audio.d2c_itype = itype;
l1audio.d2c_l1FN = L1I_GetTimeStamp();
L1Audio_Msg_DSP_INT( itype );
#if __DSP_WAKEUP_EVENT__
Audio_DSP_Wakeup_Eevent_clean();
#endif
#if defined(MT6268) //work around in 3G, there is DP_D2C_SE_DONE int. There might be error operate especially when InterRAT HO
if( itype == DP_D2C_SE_DONE && AM_IsSpeechOn() )
return;
#endif
#if defined(MT6236) || defined(MT6236B) || defined(MT6256_S00) || defined(MT6256_S01) || defined(MT6251) || defined(MT6253E) || defined(MT6253L)|| defined(MT6252) || defined(MT6252H) || defined(MT6255) || defined(MT6250) || defined(MT6260)
if(itype == D2C_DSP_DEAD_INT_ID){
#ifndef L1D_TEST
{
ASSERT_DUMP_PARAM_T dump_param;
dump_param.addr[0] = (kal_uint32)(DPRAM_CPU_base +0x0A0*2);
dump_param.len[0] = 70*2;
dump_param.addr[1] = (kal_uint32)(DPRAM2_CPU_base+0x130*2);
dump_param.len[1] = 180*2;
dump_param.addr[2] = 0; //End of dump param
EXT_ASSERT_DUMP(0, 0x20060622, 0, 0, &dump_param);
}
#else
{
extern void L1DTest_AssertFail(void);
L1DTest_AssertFail();
}
#endif
}
#endif // #if defined(MT6236) || defined(MT6236B) || defined(MT6256)
#if defined(MT6260)
{
bool dsp_ok = false;
uint32 sph_int = 0;
bool from_sph = Pseudo_SAL_DSPINT_Resolve(itype, &sph_int);
if (from_sph)
{
{
kal_int16 i;
for (i = 1; i < PSEUDO_SAL_DSPINT_PRIO_MAX; i++)
{
if (sph_int & (1 << i))
{
if (PSEUDO_SAL_DSPINT_PRIO_3G_DL == i)
{
// Do nothing. Don't trigger LISR here. 3G driver will trigger HISR by it's timing
}
else
{
L1Audio_TrigD2CHisr(DP_D2C_INT_MAPPING_BASIC + i);
}
dsp_ok |= true;
}
}
}
// After DSP send D2C and turn on bit in DP_D2C_SPEECH_UL_INT, but MCU does not receive D2C.
// Handover causes VBI reset which will clean DP_D2C_SPEECH_UL_INT
if (sph_int != 0)
{
if (!dsp_ok)
{
extern void L1D_WIN_DisableAllEvents(uint16 except_irq_mask);
DisableIRQ();
L1D_WIN_DisableAllEvents(0); // disable all TDMA events
ASSERT_REBOOT(0);
}
}
return;
}
}
L1Audio_TrigD2CHisr(itype);
#else // chip compile option
#if defined(MT6236) || defined(MT6236B) || defined(MT6256_S00) || defined(MT6256_S01) || defined(MT6251) || defined(MT6253E) || defined(MT6253L)|| defined(MT6252) || defined(MT6252H) || defined(MT6255) || defined(MT6250)
if(itype == D2C_INT6_MAGIC){
bool dsp_ok = false;
#else
if(itype == D2C_DSP_DEAD_INT_ID){
bool dsp_ok = false;
itype = *DSP_DEAD_INTERRUPT;
if( itype == D2C_DSP_DEAD_INT_ID ) {
extern void L1D_WIN_DisableAllEvents(uint16 except_irq_mask);
DisableIRQ();
*DP_D2C_TASK1 = 0; /* freeze DSP */
L1D_WIN_DisableAllEvents( 0 ); /* disable all TDMA events */
#ifndef L1D_TEST
{
ASSERT_DUMP_PARAM_T dump_param;
/* Write DSP debug info to exception record */
#if defined(MT6235) || defined(MT6235B) || defined(MT6268) || defined(MT6251)
dump_param.addr[0] = (kal_uint32)(DPRAM_CPU_base +0x0A0*2);
dump_param.len[0] = 70*2;
dump_param.addr[1] = (kal_uint32)(DPRAM2_CPU_base+0x130*2);
dump_param.len[1] = 180*2;
dump_param.addr[2] = 0; //End of dump param
#else
dump_param.addr[0] = (kal_uint32)(DPRAM_CPU_base +0x130*2);
dump_param.len[0] = 250*2;
dump_param.addr[1] = 0; //End of dump param
#endif
EXT_ASSERT_DUMP(0, 0x20060622, 0, 0, &dump_param);
}
#else
{
extern void L1DTest_AssertFail(void);
L1DTest_AssertFail();
}
#endif//#ifndef L1D_TEST
}
#endif // #if defind(MT6236)|| defined(MT6256)
#if defined(MT6250)
itype = *DSP_DACA_UL_INT;
if(itype == DP_D2C_DACA_REQ_UL){
*DSP_DACA_UL_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
itype = *DSP_DACA_DL_INT;
if(itype == DP_D2C_DACA_REQ_DL){
*DSP_DACA_DL_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#endif
itype = *DSP_PCM_REC_INT;
if( itype == D2C_UL_DL_PCM_REC_INT_ID || itype == D2C_WAV_REC_REQ_ID )
{
*DSP_PCM_REC_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
itype = *DSP_SOUND_EFFECT_INT;
if( itype == D2C_SOUND_EFFECT_INT_ID )
{
*DSP_SOUND_EFFECT_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#if defined( __BT_AUDIO_VIA_SCO__ ) && !defined(__CVSD_CODEC_SUPPORT__)
itype = *DP_AUDIO_VIA_8KBT_INT;
if( itype == D2C_AUDIO_VIA_8KBT_ID )
{
*DP_AUDIO_VIA_8KBT_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#endif
#if _SPE_FOR_TEST_SIM_
itype = *DP2_ADAPT_VOL_INT;
if( itype == DP_D2C_ADAPT_VOL )
{
*DP2_ADAPT_VOL_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#endif
if (!dsp_ok) {
extern void L1D_WIN_DisableAllEvents(uint16 except_irq_mask);
DisableIRQ();
#if !defined(MT6256_S01) && !defined(MT6255) && !defined(MT6250) && !defined(MT6260)
*DP_D2C_TASK1 = 0; /* freeze DSP */
#endif
L1D_WIN_DisableAllEvents( 0 ); /* disable all TDMA events */
ASSERT_REBOOT(0);
}
return;
}
if( (itype == DP_D2C_SE_SD_DONE) && (!AM_IsSpeechOn()) ) // when idle 16kPCM, AMR/AWB/VM record, the driver expects the D2C_SE_DONE interrupt triggered by DSP. If System's doing SMS, howerver, DSP triggers the D2C_SE_SD_DONE to MCU. Even if in this case, because the data provided by DSP is also available, the drive just easily modifies the interrupt ID to access data provide by DSP.
itype = DP_D2C_SE_DONE;
{
int32 I;
for (I = 0; I < MAX_HISR_HANDLER; I++)
{
if (itype == l1audio.hisrMagicNo[I])
{
l1audio.hisrMagicFlag |= (1<<I);
kal_activate_hisr(l1audio.hisr);
return;
}
}
}
#endif // chip compile option
#if defined(MT6235) || defined(MT6235B) || defined(MT6268) || defined(MT6253) || defined(MT6236) || defined(MT6236B) || defined(MT6256_S00)|| defined(MT6256_S01) || defined(MT6251) || defined(MT6253E) || defined(MT6253L)|| defined(MT6252) || defined(MT6252H) || defined(MT6255) || defined(MT6250) || defined(MT6260)
if (itype == DP_D2C_AVSYNC) {
Media_A2V_LISR();
} else
#endif
{
l1audio.media_flag = itype;
kal_activate_hisr(l1audio.hisr);
}
}
void L1Audio_HookHisrHandler( kal_uint16 magic_no, L1Audio_EventHandler handler, void *userData )
{
int32 I;
for( I = 0; I < MAX_HISR_HANDLER; I++ ) {
if( l1audio.hisrMagicNo[I] == 0 ) {
l1audio.hisrMagicNo[I] = magic_no;
l1audio.hisrHandler[I] = handler;
l1audio.hisrUserData[I] = userData;
break;
}
}
ASSERT_REBOOT( I != MAX_HISR_HANDLER );
}
static void UART_LISR(void)
{
uart_hisr = kal_create_hisr("UART_HISR", (kal_uint8)2, (kal_uint32)512,UART_HISR,(kal_uint8)0);
kal_activate_hisr(uart_hisr);
}
