void L1Audio_ClearFlag( uint16 audio_id ) { uint32 savedMask; if (!kal_if_hisr() && !kal_if_lisr()) kal_trace( TRACE_GROUP_AUD_MD2GCTRL, L1AUDIO_CLEARFLAG_A,audio_id,l1audio.runningState); else kal_dev_trace( TRACE_GROUP_AUD_MD2GCTRL, L1AUDIO_CLEARFLAG_A,audio_id,l1audio.runningState); kal_take_sem( l1audio.sema, KAL_INFINITE_WAIT ); ASSERT( l1audio.id_flag & (1 << audio_id) ); ASSERT( l1audio.runningState & (1 << audio_id) ); savedMask = SaveAndSetIRQMask(); l1audio.runningState &= ~(1 << audio_id); RestoreIRQMask( savedMask ); if(l1audio.runningState == 0 ) { SLEEP_UNLOCK(); } if( (l1audio.runningState == 0) && (l1audio.disallowSleepState == 0) ) { #if defined( __CENTRALIZED_SLEEP_MANAGER__ ) Audio_Wake_DSP(audio_id, KAL_FALSE); #endif } kal_give_sem( l1audio.sema ); }
void video_renderer_task_req_hdlr(ilm_struct *ilm_msg) { #if defined(__MTK_TARGET__) _video_renderer_task_local_param_t *local_para_ptr; video_renderer_task_exec_func_t exec_func; void * exec_param; ASSERT(NULL != ilm_msg); ASSERT(KAL_FALSE == kal_if_hisr()); ASSERT(KAL_FALSE == kal_if_lisr()); // get ilm parameters local_para_ptr = (_video_renderer_task_local_param_t*) ilm_msg->local_para_ptr; ASSERT(NULL != local_para_ptr); exec_func = local_para_ptr->exec_func; exec_param = &(local_para_ptr->exec_param); // do execution if (exec_func) { exec_func(exec_param); } #endif //#if defined(__MTK_TARGET__) }
/************************************************************************* * FUNCTION * mdci_deinit * * DESCRIPTION * This function de-initializes the logical channel. * * PARAMETERS * channel - logical channel * * RETURNS * MDIF error code. * *************************************************************************/ kal_int32 mdci_deinit(MDCI_CHANNEL_T channel) { kal_uint32 owner, mask; kal_int32 ret; /* error checking */ if (channel >= MDCI_MAX_CHANNEL) return MDCI_INVALID_PARAM; if (kal_if_lisr()) return MDCI_IN_LISR; /* get the current task */ owner = (kal_uint32)kal_get_current_thread_ID(); /* check owner */ if (mdci_ctrl_pool[channel].owner != owner) { return MDCI_NOT_OWNER; } ret = MDCI_SUCCESS; /* check state */ mask = SaveAndSetIRQMask(); if (mdci_ctrl_pool[channel].state != MDCI_IDLE) { ret = MDCI_IN_USE; } else { /* free the channel */ mdci_ctrl_pool[channel].owner = 0; } RestoreIRQMask(mask); return ret; }
void drv_trace4(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1, kal_uint32 data2, kal_uint32 data3, kal_uint32 data4) { if (INT_QueryExceptionStatus()) return; if(kal_if_lisr() == KAL_TRUE) return; if(kal_if_hisr()) { kal_dev_trace(trc_class, msg_index, arg_type, data1, data2, data3, data4); } else { kal_trace(trc_class, msg_index, arg_type, data1, data2, data3, data4); } }
void sherif_or_dump(kal_uint16* pAddr, kal_uint16 uValue, char* file_p, long line_p) { uint32 savedMask; if(!kal_if_lisr()) { kal_wap_trace(MOD_L1SP, TRACE_INFO, "[SHERIF][%d]or= [*%x]=%x, at: %s, line: %d",uSherifWriteCount, pAddr, uValue, file_p, line_p); } *pAddr |= uValue; savedMask = SaveAndSetIRQMask(); SHERIF_DUMP_ADDR[uSherifWriteIndex] = (kal_uint32)pAddr; SHERIF_DUMP_VALUE[uSherifWriteIndex] = *pAddr; SHERIF_DUMP_COUNT[uSherifWriteIndex++] = uSherifWriteCount++; if(uSherifWriteIndex>=SHERIF_DUMP_LENGTH) { uSherifWriteIndex = 0; } RestoreIRQMask(savedMask); }
void idp_init(void) { kal_uint32 i; /* All operations based on this buffer will assume that the size of the buffer * is power of 2. This is to say that I have to ensure that the binary form of * buffer_size must contain only one one. */ //ASSERT(1 == count_one_bit_number(IDP_TRACED_BUFFER_SIZE)); /* Because I need to call semaphore API, I have to ensure * this function will not be called from HISR & LISR. */ if (kal_if_hisr() || kal_if_lisr()) { ASSERT(0); } idp_owners_sem = kal_create_sem("IDP", 1); for (i = 0; i < MAX_CONCURRENT_DP; ++i) { memset(&(owners[i]), 0, sizeof(owners[i])); } idp_hw_init(); #if defined(IDP_HISR_SUPPORT) idp_hisr_init(); #endif #if defined(DRV_IDP_6238_SERIES) || defined(DRV_IDP_MT6236_SERIES) // For MT6268 VT video frame rotation //idp_sw_yuv_rotator_init(); // for MT6268 VT #endif // #if defined(DRV_IDP_6238_SERIES) || defined(DRV_IDP_MT6236_SERIES) }
/************************************************************************* * FUNCTION * mdci_owner_init * * DESCRIPTION * This function initializes the logical channel for the specified task. * * PARAMETERS * channel - logical channel * task - owner task * funp - ISR callback function * * RETURNS * MDIF error code. * *************************************************************************/ kal_int32 mdci_owner_init(MDCI_CHANNEL_T channel, kal_taskid task, MDCI_CALLBACK funp) { kal_uint32 owner, mask; kal_int32 ret; /* error checking */ if (channel >= MDCI_MAX_CHANNEL) return MDCI_INVALID_PARAM; if (funp == NULL) return MDCI_INVALID_PARAM; if (kal_if_lisr()) return MDCI_IN_LISR; ret = MDCI_SUCCESS; owner = (kal_uint32)task; /* check if the channel is free */ mask = SaveAndSetIRQMask(); if (mdci_ctrl_pool[channel].owner != 0) { ret = MDCI_IN_USE; } else { mdci_ctrl_pool[channel].owner = owner; } RestoreIRQMask(mask); if (ret != MDCI_SUCCESS) return ret; /* initialize the control block */ mdci_ctrl_pool[channel].state = MDCI_IDLE; kal_mem_set(&(mdci_ctrl_pool[channel].buff), 0, sizeof(MDCI_BUFF_T)); mdci_ctrl_pool[channel].funp = funp; return ret; }
static void Audio_Wake_DSP(uint16 audio_id, kal_bool flag) { if (!kal_if_hisr() && !kal_if_lisr()) kal_trace( TRACE_GROUP_AUD_MD2GCTRL, L1AUDIO_MD2G_PWR_CTRL, audio_id, flag); else kal_dev_trace( TRACE_GROUP_AUD_MD2GCTRL, L1AUDIO_MD2G_PWR_CTRL, audio_id, flag); if(flag) { #if defined(MT6260) RM_Resource_Control (RM_MODEM_DSP_1, flag); #else Audio_SW_CPD_Event_Setting(flag); Audio_SW_CPD_Eevent_ChangeMode(flag); #endif #if defined(MTK_SLEEP_ENABLE) #if defined(__AUDIO_POWERON_RESET_DSP__) { extern void AFE_RegisterStore(void); AFE_RegisterStore(); //restore AFE register } { unsigned short DSP_status; DSP_status = L1D_Audio_RestartDSP(); ASSERT(!DSP_status); } #else L1SM_IntSleepDisable( l1audio.l1sm_handle ); L1SM_Multi_SW_WakeUp(); L1D_MD2G_PWD_Disable(l1audio.md2g_pdn_handle); L1SM_IntSleepEnable( l1audio.l1sm_handle ); #endif #endif Audio_DSP_Wakeup_Eevent_Setting(flag); l1audio.audio_cpd_count++; l1audio.audio_cpd_count_current++; } else { Audio_DSP_Wakeup_Eevent_Setting(flag); #if defined(MTK_SLEEP_ENABLE) #if defined(__AUDIO_POWERON_RESET_DSP__) L1D_Audio_NoNeedDSP(); AFE_RegisterBackup(); //Backup AFE register #else L1D_MD2G_PWD_Enable(l1audio.md2g_pdn_handle); #endif #endif #if defined(MT6260) RM_Resource_Control (RM_MODEM_DSP_1, flag); #else Audio_SW_CPD_Eevent_ChangeMode(flag); #endif l1audio.audio_cpd_count_current--; #if __DSP_WAKEUP_EVENT__ Audio_DSP_Wakeup_Eevent_clean(); #endif } if (!kal_if_hisr() && !kal_if_lisr()) kal_trace( TRACE_GROUP_AUD_MD2GCTRL, L1AUDIO_MD2G_PWR_CTRL_DONE, audio_id, flag); else kal_dev_trace( TRACE_GROUP_AUD_MD2GCTRL, L1AUDIO_MD2G_PWR_CTRL_DONE, audio_id, flag); }
/************************************************************************* * FUNCTION * mdci_read * * DESCRIPTION * This function reads data through either mailbox channel or stream * channel. * * PARAMETERS * channel - logical channel * buff - pointer to channel buffer * * RETURNS * MDIF error code. * *************************************************************************/ kal_int32 mdci_read(MDCI_CHANNEL_T channel, MDCI_BUFF_T *buff) { kal_uint32 owner, mask, ret, event; kal_char event_name[20]; #ifdef __IVP__ dbg_print("Error.... can not use mdci_read in IVP\n\r"); while(1); #endif /* check if a LISR is running */ if (kal_if_lisr()) return MDCI_IN_LISR; /* check parameters */ if (channel >= MDCI_MAX_CHANNEL) return MDCI_INVALID_PARAM; if (buff == NULL) return MDCI_INVALID_PARAM; /* get the current task */ owner = (kal_uint32)kal_get_current_thread_ID(); /* check owner */ if (mdci_ctrl_pool[channel].owner != owner && mdci_is_chanel_need_check_owner(channel)) { return MDCI_NOT_OWNER; } /* create an event for the first use */ if (mdci_ctrl_pool[channel].event == NULL) { sprintf(event_name, "MDIF%d event", channel); mdci_ctrl_pool[channel].event = kal_create_event_group(event_name); if (mdci_ctrl_pool[channel].event == NULL) ASSERT(0); } /* check state */ ret = MDCI_SUCCESS; mask = SaveAndSetIRQMask(); if (mdci_ctrl_pool[channel].state != MDCI_IDLE) { ret = MDCI_IN_USE; } else { /* set ACTIVE_WRITE */ mdci_ctrl_pool[channel].state = MDCI_ACTIVE_READ; } RestoreIRQMask(mask); if (ret != MDCI_SUCCESS) return ret; #ifndef __IVP__ /* wait for the event */ kal_retrieve_eg_events(mdci_ctrl_pool[channel].event, 1, KAL_OR_CONSUME, &event, KAL_SUSPEND); #endif if (event != 1) { ASSERT(0); } /* read channel buffer */ memcpy(buff, &(mdci_ctrl_pool[channel].buff), sizeof(MDCI_BUFF_T)); /* set ACTIVE_IDLE */ mdci_ctrl_pool[channel].state = MDCI_IDLE; return MDCI_SUCCESS; }
__attribute__((section ("INTSRAM_ROCODE"))) kal_int32 mdci_write_internal(MDCI_CHANNEL_T channel, MDCI_BUFF_T *buff,kal_bool check_lisr) { kal_uint32 owner, mask, mdci_busy, phy_chann, saveaddr = 0; kal_int32 ret; MDCI_BUFF_T *chdata; /* check if a LISR is running */ if (1 == check_lisr) { if (kal_if_lisr()) { mask = SaveAndSetIRQMask(); mdci_err_log[log_index].return_tick = kal_get_systicks(); mdci_err_log[log_index].return_value = MDCI_IN_LISR; log_index++; log_index %= DebugEntryNo; RestoreIRQMask(mask); return MDCI_IN_LISR; } } /* check parameters */ if (channel >= MDCI_MAX_CHANNEL) { mask = SaveAndSetIRQMask(); mdci_err_log[log_index].return_tick = kal_get_systicks(); mdci_err_log[log_index].return_value = MDCI_INVALID_PARAM; log_index++; log_index %= DebugEntryNo; RestoreIRQMask(mask); return MDCI_INVALID_PARAM; } if (buff == NULL) { mask = SaveAndSetIRQMask(); mdci_err_log[log_index].return_tick = kal_get_systicks(); mdci_err_log[log_index].return_value = MDCI_INVALID_PARAM; log_index++; log_index %= DebugEntryNo; RestoreIRQMask(mask); return MDCI_INVALID_PARAM; } /* get the current task */ owner = (kal_uint32)kal_get_current_thread_ID(); /* check owner */ if (mdci_ctrl_pool[channel].owner != owner && mdci_is_chanel_need_check_owner(channel) ) { mask = SaveAndSetIRQMask(); mdci_err_log[log_index].return_tick = kal_get_systicks(); mdci_err_log[log_index].return_value = MDCI_NOT_OWNER; log_index++; log_index %= DebugEntryNo; RestoreIRQMask(mask); return MDCI_NOT_OWNER; } /* check state */ ret = MDCI_SUCCESS; mask = SaveAndSetIRQMask(); if (mdci_ctrl_pool[channel].state != MDCI_IDLE) { ret = MDCI_IN_USE; } else { /* set ACTIVE_WRITE */ mdci_ctrl_pool[channel].state = MDCI_ACTIVE_WRITE; } RestoreIRQMask(mask); if (ret != MDCI_SUCCESS) { mask = SaveAndSetIRQMask(); mdci_err_log[log_index].return_tick = kal_get_systicks(); mdci_err_log[log_index].return_value = ret; log_index++; log_index %= DebugEntryNo; RestoreIRQMask(mask); return ret; } /* get one physical channel */ mask = SaveAndSetIRQMask(); mdci_busy = *MDIF_BUSY; //for (phy_chann = 0; phy_chann < MDIF_MAX_PHY; phy_chann++) { for (phy_chann = mdci_writeindx_for_FC ; phy_chann < (mdci_writeindx_for_FC + MDIF_MAX_PHY); phy_chann++) { phy_chann %= MDIF_MAX_PHY; if (mdci_busy & (1 << phy_chann)) { //continue; mdci_err_log[log_index].return_tick = kal_get_systicks(); mdci_err_log[log_index].return_value = MDCI_NO_PHY_CHANNEL; mdci_err_log[log_index].return_busy = mdci_busy; mdci_err_log[log_index].return_write_index = mdci_writeindx_for_FC; log_index++; log_index %= DebugEntryNo; RestoreIRQMask(mask); mdci_ctrl_pool[channel].state = MDCI_IDLE; return MDCI_NO_PHY_CHANNEL; //break; } else { /* set BUSY bit */ *MDIF_BUSY = (1 << phy_chann); mdci_writeindx_for_FC = (phy_chann + 1)%MDIF_MAX_PHY; break; } } /* set logical channel number */ buff->channel = channel; #ifndef __IVP__ mdci_trans_log_pool[channel][mdci_trans_log_index[channel]].tick = kal_get_systicks(); #endif /* __IVP__ */ /* add a MD offset for the stream buffer address */ if (!MDCI_IS_MAILBOX(buff)) { saveaddr = MDCI_STREAM_ADDR(buff); #if defined(MDIF_FOR_AP_SIDE) MDCI_STREAM_ADDR(buff) |= mdci_md_offset; #else /* MDIF_FOR_AP_SIDE */ MDCI_STREAM_ADDR(buff) &= ~mdci_md_offset; #endif /* MDIF_FOR_AP_SIDE */ } /* copy channel buffer */ chdata = (MDCI_BUFF_T *)MDIF_TXCHDATA + phy_chann; kal_mem_cpy(chdata, buff, sizeof(MDCI_BUFF_T)); /* restore the stream buffer address */ if (!MDCI_IS_MAILBOX(buff)) { MDCI_STREAM_ADDR(buff) = saveaddr; } /* start MDIF */ *MDIF_TCHNUM = phy_chann; /* set ACTIVE_IDLE */ mdci_ctrl_pool[channel].state = MDCI_IDLE; RestoreIRQMask(mask); /* do transaction log */ kal_mem_cpy(&(mdci_ctrl_pool[channel].buff), buff, sizeof(MDCI_BUFF_T)); kal_mem_cpy(&(mdci_trans_log_pool[channel][mdci_trans_log_index[channel]].ct), &mdci_ctrl_pool[channel], sizeof(MDCI_CTRL_T)); mdci_trans_log_index[channel]++; mdci_trans_log_index[channel]%=(DebugEntryNo); return MDCI_SUCCESS; }
kal_int32 idp_add_traced_begin(IdpTracedAPI const api) { kal_uint32 savedMask; kal_int32 my_idx; #if defined(ENABLE_LOGGING_FOR_IS_BUSY) kal_int32 my_idx_minus_1; kal_int32 my_idx_minus_2; #endif #if !defined(ENABLE_LOGGING_FOR_IS_BUSY) switch (api) { case IDP_TRACED_API_camera_preview_IS_BUSY: case IDP_TRACED_API_camera_preview_with_face_detection_IS_BUSY: case IDP_TRACED_API_camera_capture_to_jpeg_IS_BUSY: case IDP_TRACED_API_camera_capture_to_mem_IS_BUSY: case IDP_TRACED_API_camera_capture_to_barcode_IS_BUSY: case IDP_TRACED_API_jpeg_decode_IS_BUSY: case IDP_TRACED_API_jpeg_encode_IS_BUSY: case IDP_TRACED_API_jpeg_resize_IS_BUSY: case IDP_TRACED_API_image_resize_IS_BUSY: case IDP_TRACED_API_rgb2yuv_IS_BUSY: case IDP_TRACED_API_video_editor_decode_IS_BUSY: case IDP_TRACED_API_video_editor_encode_IS_BUSY: case IDP_TRACED_API_video_decode_IS_BUSY: case IDP_TRACED_API_video_encode_IS_BUSY: case IDP_TRACED_API_webcam_IS_BUSY: case IDP_TRACED_API_video_call_decode_IS_BUSY: case IDP_TRACED_API_video_call_encode_IS_BUSY: case IDP_TRACED_API_simple_display_with_rotate_IS_BUSY: case IDP_TRACED_API_image_effect_pixel_IS_BUSY: return -1; //break; default: break; } #endif savedMask = SaveAndSetIRQMask(); { my_idx = g_idp_traced_curr_idx; #if defined(ENABLE_LOGGING_FOR_IS_BUSY) // I don't want the same xxx_IS_BUSY fill out of my // g_idp_traced space. switch (my_idx) { case 0: my_idx_minus_1 = (IDP_TRACED_BUFFER_SIZE - 1); my_idx_minus_2 = (IDP_TRACED_BUFFER_SIZE - 2); break; case 1: my_idx_minus_1 = 0; my_idx_minus_2 = (IDP_TRACED_BUFFER_SIZE - 1); break; default: my_idx_minus_1 = (my_idx - 1); my_idx_minus_2 = (my_idx - 2); break; } switch (api) { case IDP_TRACED_API_camera_preview_IS_BUSY: case IDP_TRACED_API_camera_preview_with_face_detection_IS_BUSY: case IDP_TRACED_API_camera_capture_to_jpeg_IS_BUSY: case IDP_TRACED_API_camera_capture_to_mem_IS_BUSY: case IDP_TRACED_API_camera_capture_to_barcode_IS_BUSY: case IDP_TRACED_API_camera_capture_to_ybuffer_IS_BUSY: case IDP_TRACED_API_jpeg_decode_IS_BUSY: case IDP_TRACED_API_jpeg_encode_IS_BUSY: case IDP_TRACED_API_jpeg_resize_IS_BUSY: case IDP_TRACED_API_image_resize_IS_BUSY: case IDP_TRACED_API_rgb2yuv_IS_BUSY: case IDP_TRACED_API_video_editor_decode_IS_BUSY: case IDP_TRACED_API_video_editor_encode_IS_BUSY: case IDP_TRACED_API_video_decode_IS_BUSY: case IDP_TRACED_API_video_encode_IS_BUSY: case IDP_TRACED_API_webcam_IS_BUSY: case IDP_TRACED_API_video_call_decode_IS_BUSY: case IDP_TRACED_API_video_call_encode_IS_BUSY: case IDP_TRACED_API_simple_display_with_rotate_IS_BUSY: case IDP_TRACED_API_image_effect_pixel_IS_BUSY: if ((api == g_idp_traced[my_idx_minus_1].m_api) && (api == g_idp_traced[my_idx_minus_2].m_api)) { RestoreIRQMask(savedMask); return my_idx_minus_1; } break; default: break; } #endif ++g_idp_traced_curr_idx; g_idp_traced_curr_idx &= (IDP_TRACED_BUFFER_SIZE - 1); } RestoreIRQMask(savedMask); g_idp_traced[my_idx].m_api = api; g_idp_traced[my_idx].m_who = kal_get_current_thread_ID(); if (kal_if_hisr()) { g_idp_traced[my_idx].m_call_by_which_level = IDP_CALL_BY_HISR; } else if (kal_if_lisr()) { g_idp_traced[my_idx].m_call_by_which_level = IDP_CALL_BY_LISR; } else { g_idp_traced[my_idx].m_call_by_which_level = IDP_CALL_BY_TASK; } g_idp_traced[my_idx].m_done = KAL_FALSE; g_idp_traced[my_idx].m_start_time_drv = drv_get_current_time(); return my_idx; }
HIF_RESULT hif_dma_read_internal(HIF_HANDLE handle, HIF_TYPE type, kal_uint32 addr, kal_uint32 size, HIF_CALLBACK fCB) { HIF_RESULT result = HIF_RESULT_OK; HIF_INTERNAL_HANDLE_T* pHandle = (HIF_INTERNAL_HANDLE_T*) handle; kal_uint32 retrieved_events; // Enable HIF interrupt. ENABLE_HIF_INTR(pHandle->engine_id); pHandle->DMA_BUSY = KAL_TRUE; #ifdef MTK_SLEEP_ENABLE L1SM_SleepDisable(hif_sleepMode_handle[pHandle->engine_id]);//unlock MD sleep mode #endif if (fCB == NULL) { if(!(kal_if_lisr()||kal_if_hisr())) { //Clear the evnet for pHandle->engine_id HIF for task level kal_set_eg_events(hif_events, ~(1 << pHandle->engine_id), KAL_AND); } else ASSERT(0); //HIF DMA blocking mode is not allowed in LISR or HISR } // Setup HIF. //SET_HIF_BUS_WIDTH(pHandle->engine_id, pHandle->config.hif_bus_width); SET_HIF_READ(pHandle->engine_id); if(type == HIF_TYPE_A0H_DMA) { SET_HIF_A0_HIGH(pHandle->engine_id); } else if(type == HIF_TYPE_A0L_DMA) { SET_HIF_A0_LOW(pHandle->engine_id); } SET_HIF_DAMOUNT(pHandle->engine_id, size); /* // Set DMA address. PDMA_SET_BUF_ADDR(pHandle->engine_id, addr); PDMA_SET_RW_DIRECTION(pHandle->engine_id, 1); // 1:read; 0: write PDMA_SET_BUF_LEN(pHandle->engine_id, size); PDMA_SET_BURST_LEN(pHandle->engine_id, 7); PDMA_START(pHandle->engine_id); //Start DMA */ //dma config SLA_CustomLogging("HDM",1);//set for debug #if (defined(MT6752) && !defined(__ANDROID_MODEM__)) hif_dma_menu[pHandle->engine_id].addr = addr + 0x80000000; #else hif_dma_menu[pHandle->engine_id].addr = addr; #endif hif_dma_input[pHandle->engine_id].count = (pHandle->config.hif_bus_width == 16) ? (size >> 1) : size; hif_dma_input[pHandle->engine_id].type = DMA_HWRX; hif_dma_input[pHandle->engine_id].size = (pHandle->config.hif_bus_width == 16) ? DMA_SHORT : DMA_BYTE; hif_dma_input[pHandle->engine_id].callback = NULL; hif_dma_input[pHandle->engine_id].menu = (void*) &hif_dma_menu[pHandle->engine_id]; DMA_Config(hif_sysdma_id[pHandle->engine_id], &hif_dma_input[pHandle->engine_id], KAL_TRUE); // Set fCB as HIF interrupt callback. hif_cb[pHandle->engine_id] = fCB; // Start HIF START_HIF(pHandle->engine_id); if (fCB == NULL) { if(!(kal_if_lisr()||kal_if_hisr())) { kal_retrieve_eg_events(hif_events, (1<<pHandle->engine_id), KAL_OR_CONSUME, &retrieved_events, KAL_SUSPEND); pHandle->DMA_BUSY = KAL_FALSE; } else ASSERT(0); //HIF DMA blocking mode is not allowed in LISR or HISR } return result; }
kal_bool idp_close( kal_uint32 const key, idp_close_hook_t const hook) { kal_bool result; idp_owner_t *owner = NULL; result = idp_find(key, &owner); if (KAL_FALSE == result) { //ASSERT(0); return KAL_FALSE; } result = hook(owner); owner->key = 0; /* Because I need to call semaphore API, I have to ensure * this function will not be called from HISR & LISR. */ if (kal_if_hisr()) { //ASSERT(0); return KAL_FALSE; } if (kal_if_lisr()) { //ASSERT(0); return KAL_FALSE; } #if ((!defined(DRV_IDP_6252_SERIES)) && (!defined(DRV_IDP_6253_SERIES))) // To see if there is no one use IDP. { kal_uint32 i; kal_bool can_poweroff = KAL_TRUE; // lock all possible data paths. kal_take_sem(idp_owners_sem, KAL_INFINITE_WAIT); for (i = 0; i < MAX_CONCURRENT_DP; ++i) { if (owners[i].key != 0) { // There at least one uses IDP now, so I can not // power off IDP. can_poweroff = KAL_FALSE; } } if (KAL_TRUE == can_poweroff) { #if defined(IDP_DRVPDN_SUPPORT) turn_off_idp_power(); #endif } // unlock all possible data paths. kal_give_sem(idp_owners_sem); } #endif // ((!defined(DRV_IDP_6252_SERIES))... return KAL_TRUE; }
kal_bool idp_find_empty_and_register( kal_uint32 * const key, idp_owner_t ** const owner) { kal_uint32 i; kal_bool result = KAL_FALSE; if (NULL == owner) { //ASSERT(0); return KAL_FALSE; } /* Because I need to call semaphore API, I have to ensure * this function will not be called from HISR & LISR. */ if (kal_if_hisr()) { //ASSERT(0); return KAL_FALSE; } if (kal_if_lisr()) { //ASSERT(0); return KAL_FALSE; } kal_take_sem(idp_owners_sem, KAL_INFINITE_WAIT); for (i = 0; i < MAX_CONCURRENT_DP; ++i) { //kal_bool find_one = KAL_FALSE; if (0 == owners[i].key) { kal_uint32 local_key; while (1) { kal_bool cal_again = KAL_FALSE; local_key = 0; while (0 == local_key) { local_key = rand(); } { int j; for (j = 0; j < MAX_CONCURRENT_DP; ++j) { if (j != i) { if (owners[j].key == local_key) { cal_again = KAL_TRUE; } if (KAL_TRUE == cal_again) { break; } } } } if (KAL_FALSE == cal_again) { break; } } owners[i].key = local_key; (*key) = local_key; owners[i].task = kal_get_current_thread_ID(); (*owner) = &(owners[i]); result = KAL_TRUE; //find_one = KAL_TRUE; break; } //if (KAL_TRUE == find_one) //{ // break; //} } kal_give_sem(idp_owners_sem); return result; }
/************************************************************************* * FUNCTION * i2c_read * * DESCRIPTION * This function read bytes from specified registers through SCCB interface * * PARAMETERS * owner : Who wants to read bytes * para : read buffer of reading the specified register from device * datalen: Number of bytes to read in one transfer * transfer_num: Number of transfer in this transaction * * RETURNS * None *************************************************************************/ SCCB_TRANSACTION_RESULT i2c_cont_read(SCCB_OWNER owner,kal_uint8* para,kal_uint32 transfer_num,kal_uint32 datalen) { register sccb_handle_struct* handle=&sccb_handle[owner]; register sccb_config_struct* config=&handle->sccb_config; register kal_uint32 count; kal_uint32 savedMask; ASSERT(owner<SCCB_NUM_OF_OWNER); if(kal_if_lisr()) ASSERT(0); count=datalen*transfer_num; #if(defined (I2C_DMA_ENABLED)) //if u want a transcation with len>8, please enable DMA. if((!config->is_DMA_enabled) && count>8) ASSERT(0); #else if(count>8) ASSERT(0); #endif //if(handle->transaction_mode==SCCB_TRANSACTION_HIGH_SPEED_MODE && config->delay_len!=0) //ASSERT(0); //Multi-transfer with STOP condition can't be applied to high speed mode. savedMask=i2c_wait_transaction_complete_and_lock(owner); if(i2c_status.owner!=owner) { if(config->get_handle_wait) {ASSERT(0);} else return SCCB_TRANSACTION_FAIL; } i2c_status.read_buffer=para; CLEAR_I2C_FIFO; CLEAR_I2C_STA; ENABLE_I2C_INT; SET_I2C_SLAVE_ADDRESS(config->slave_address,I2C_READ_BIT); SET_I2C_TRANSFER_LENGTH(datalen); SET_I2C_TRANSACTION_LENGTH(transfer_num); SET_I2C_STEP_CNT_DIV(handle->fs_step_cnt_div); SET_I2C_SAMPLE_CNT_DIV(handle->fs_sample_cnt_div); if(handle->sccb_config.transaction_mode==SCCB_TRANSACTION_FAST_MODE) { SET_I2C_FAST_MODE; if(config->delay_len>0) { SET_I2C_ST_BETWEEN_TRANSFER; SET_I2C_DELAY_LENGTH(config->delay_len-1); } else { SET_I2C_RS_BETWEEN_TRANSFER; } } else if(handle->sccb_config.transaction_mode==SCCB_TRANSACTION_HIGH_SPEED_MODE) { SET_I2C_HS_STEP_CNT_DIV(handle->hs_step_cnt_div); SET_I2C_HS_SAMPLE_CNT_DIV(handle->hs_sample_cnt_div); SET_I2C_HS_MODE; SET_I2C_RS_BETWEEN_TRANSFER; } else ASSERT(0); DISABLE_I2C_DIR_CHANGE; #if(defined (I2C_DMA_ENABLED)) i2c_status.is_DMA_enabled=config->is_DMA_enabled; if(i2c_status.is_DMA_enabled) { i2c_status.number_of_read=0; ENABLE_I2C_DMA_TRANSFER; /*DMA Setting*/ I2C_STOP_DMA_TRANSFER(5); I2C_SET_RX_DMA_CONTROL(5,DMA_MASTER_I2C_RX); I2C_SET_DMA_PROGRAMMABLE_ADDR(5,(kal_uint32)para); I2C_SET_DMA_TRANSFER_COUNT(5,count); I2C_START_DMA_TRANSFER(5); } else #endif { i2c_status.number_of_read=count; DISABLE_I2C_DMA_TRANSFER; } START_I2C_TRANSACTION; #if defined(I2C_DEBUG) ContRLT[ContRLT_C]=DRV_Reg(0x80200000)-LT; if(ContRLT[ContRLT_C]>0 && ContRLT[ContRLT_C]>WorstContRLT) WorstContRLT=ContRLT[ContRLT_C]; ContRLT_C++; ContRLT_C&=I2C_LOG; #endif RestoreIRQMask(savedMask); // !! After the configuration, clear the I bit.!! i2c_wait_transaction_complete(); return handle->transaction_result; }
/************************************************************************* * FUNCTION * i2c_write_and_read * * DESCRIPTION * This function write command to devices through SCCB interface, and then read bytes from it. * * PARAMETERS * owner : Who wants to read bytes * R_buffer: The reading buffer of command to write * R_len: The length of R_buffer * W_buffer: The writing buffer of data whcih are read from device registers * W_len: The length of W_buffer * * RETURNS * None *************************************************************************/ SCCB_TRANSACTION_RESULT i2c_write_and_read(SCCB_OWNER owner,kal_uint8* in_buffer,kal_uint32 in_len,kal_uint8* out_buffer,kal_uint32 out_len) { register sccb_handle_struct* handle=&sccb_handle[owner]; register sccb_config_struct* config=&handle->sccb_config; kal_uint32 savedMask,i; ASSERT(owner<SCCB_NUM_OF_OWNER); if(kal_if_lisr()) ASSERT(0); #if(defined (I2C_DMA_ENABLED)) if((!config->is_DMA_enabled) && (out_len>8 || in_len>8)) ASSERT(0); #else if(out_len>8 || in_len>8) //if u want a transcation with len>8, please enable DMA. ASSERT(0); #endif savedMask=i2c_wait_transaction_complete_and_lock(owner); if(i2c_status.owner!=owner) { if(config->get_handle_wait) {ASSERT(0);} else return SCCB_TRANSACTION_FAIL; } i2c_status.read_buffer=out_buffer; CLEAR_I2C_FIFO; CLEAR_I2C_STA; ENABLE_I2C_INT; SET_I2C_SLAVE_ADDRESS(config->slave_address,I2C_WRITE_BIT); SET_I2C_TRANSFER_LENGTH(in_len); SET_I2C_AUX_TRANSFER_LENGTH(out_len); SET_I2C_RS_BETWEEN_TRANSFER; SET_I2C_TRANSACTION_LENGTH(2); ENABLE_I2C_DIR_CHANGE; SET_I2C_STEP_CNT_DIV(handle->fs_step_cnt_div); SET_I2C_SAMPLE_CNT_DIV(handle->fs_sample_cnt_div); if(handle->sccb_config.transaction_mode==SCCB_TRANSACTION_FAST_MODE) { SET_I2C_FAST_MODE; //SET_I2C_ST_BETWEEN_TRANSFER; } else if(handle->sccb_config.transaction_mode==SCCB_TRANSACTION_HIGH_SPEED_MODE) { SET_I2C_HS_STEP_CNT_DIV(handle->hs_step_cnt_div); SET_I2C_HS_SAMPLE_CNT_DIV(handle->hs_sample_cnt_div); SET_I2C_HS_MODE; //SET_I2C_RS_BETWEEN_TRANSFER; } else ASSERT(0); #if(defined (I2C_DMA_ENABLED)) i2c_status.is_DMA_enabled=config->is_DMA_enabled; if(i2c_status.is_DMA_enabled) { i2c_status.number_of_read=0; ENABLE_I2C_DMA_TRANSFER; //DMA Setting I2C_STOP_DMA_TRANSFER(4); I2C_SET_TX_DMA_CONTROL(4,DMA_MASTER_I2C_TX); I2C_SET_DMA_PROGRAMMABLE_ADDR(4,(kal_uint32)in_buffer); I2C_SET_DMA_TRANSFER_COUNT(4,in_len); I2C_START_DMA_TRANSFER(4); I2C_STOP_DMA_TRANSFER(5); I2C_SET_RX_DMA_CONTROL(5,DMA_MASTER_I2C_RX); I2C_SET_DMA_PROGRAMMABLE_ADDR(5,(kal_uint32)out_buffer); I2C_SET_DMA_TRANSFER_COUNT(5,out_len); I2C_START_DMA_TRANSFER(5); } else #endif { i2c_status.number_of_read=out_len; DISABLE_I2C_DMA_TRANSFER; for(i=0;i<in_len;i++) { REG_I2C_DATA_PORT=*(in_buffer+i); } } START_I2C_TRANSACTION; #if defined(I2C_DEBUG) WRLT[WRLT_C]=DRV_Reg(0x80200000)-LT; if(WRLT[WRLT_C]>0 && WRLT[WRLT_C]>WorstWRLT) { WorstWRLT=WRLT[WRLT_C]; Wbase=LT; Wcount= WRLT_C; } WRLT_C++; WRLT_C&=I2C_LOG; #endif RestoreIRQMask(savedMask); // !! After the configuration, clear the I bit.!! i2c_wait_transaction_complete(); return handle->transaction_result; }
void idp_internal_crz_usel_dsel(kal_uint32 scenario, kal_uint32 source_w, kal_uint32 source_h, kal_uint32 target_w, kal_uint32 target_h, kal_uint32* usel, kal_uint32* dsel) { idp_custom_crz_usel_dsel(((CUSTOM_SCENARIO_ID)scenario), (source_w), (source_h), (target_w), (target_h), (usel), (dsel)); if ((INT_QueryExceptionStatus() == KAL_FALSE) && (kal_if_hisr() == KAL_FALSE) && (kal_if_lisr() == KAL_FALSE)) { kal_trace(TRACE_INFO, IDP_CUSTOM_CRZ_U_D, (scenario), (source_w), (source_h), (target_w), (target_h), *(usel), *(dsel)); } }