void __init exynos5_universal5420_display_init(void)
{
struct resource *res;
struct clk *mout_mdnie1;
struct clk *mout_mpll;
/* GPIO CONFIG */
gpio_request(GPIO_LCD_EN, "LCD_EN");
gpio_request_one(GPIO_TCON_RDY, GPIOF_IN, "TCON_RDY");
gpio_request(GPIO_TCON_INTR, "TCON_INTR");
s3c_gpio_setpull(GPIO_TCON_INTR, S3C_GPIO_PULL_DOWN);
s5p_register_gpio_interrupt(GPIO_TCON_INTR);
tcon_irq = gpio_to_irq(GPIO_TCON_INTR);
#if defined(CONFIG_FB_HW_TRIGGER)
gpio_request(GPIO_PSR_TE, "PSR_TE");
s3c_gpio_cfgpin(GPIO_PSR_TE, S3C_GPIO_SFN(2));
#endif
s5p_dsim1_set_platdata(&dsim_platform_data);
s5p_fimd1_set_platdata(&chagall_lcd1_pdata);
s5p_mic_set_platdata(&chagall_fb_win0);
platform_add_devices(chagall_display_devices,
ARRAY_SIZE(chagall_display_devices));
mout_mdnie1 = clk_get(NULL, "mout_mdnie1");
if ((IS_ERR(mout_mdnie1)))
pr_err("Can't get clock[%s]\n", "mout_mdnie1");
mout_mpll = clk_get(NULL, "mout_mpll");
if ((IS_ERR(mout_mpll)))
pr_err("Can't get clock[%s]\n", "mout_mpll");
if (mout_mdnie1 && mout_mpll)
clk_set_parent(mout_mdnie1, mout_mpll);
if (mout_mdnie1)
clk_put(mout_mdnie1);
if (mout_mpll)
clk_put(mout_mpll);
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mdnie1", 266 * MHZ);
keep_lcd_clk(&s5p_device_fimd1.dev, 1);
res = platform_get_resource(&s5p_device_fimd1, IORESOURCE_MEM, 1);
if (res) {
res->start = bootloaderfb_start;
res->end = res->start + bootloaderfb_size - 1;
pr_info("bootloader fb located at %8X-%8X\n", res->start, res->end);
} else {
pr_err("failed to find bootloader fb resource\n");
}
}
void __init exynos5_universal5410_display_init(void)
{
struct resource *res;
#if defined(CONFIG_LCD_MIPI_S6E8FA0)
unsigned int lcd_id = lcdtype & 0xF;
if (!gpio_get_value(GPIO_OLED_ID)) {
dsim_info.dsim_ddi_pd = &ea8062_mipi_lcd_driver;
pr_err("panel M\n");
} else {
if (lcd_id == 1 || lcd_id == 2) {
dsim_info.dsim_ddi_pd = &s6e8fa0_mipi_lcd_driver;
pr_err("panel A,B,C\n");
} else if (lcd_id == 3 || lcd_id == 4) {
dsim_info.dsim_ddi_pd = &s6e8fa0_6P_mipi_lcd_driver;
pr_err("panel D,E,F\n");
} else if (lcd_id == 5 || lcd_id == 6) {
dsim_info.dsim_ddi_pd = &s6e8fa0_G_mipi_lcd_driver;
pr_err("panel G\n");
} else if (lcd_id == 7) {
dsim_info.dsim_ddi_pd = &s6e8fa0_I_mipi_lcd_driver;
pr_err("panel I\n");
} else {
dsim_info.dsim_ddi_pd = &s6e8fa0_I_mipi_lcd_driver;
pr_err("panel select fail\n");
}
}
#elif defined(CONFIG_LCD_MIPI_S6E3FA0)
dsim_info.dsim_ddi_pd = &s6e3fa0_mipi_lcd_driver;
#endif
#ifdef CONFIG_FB_MIPI_DSIM
s5p_dsim1_set_platdata(&dsim_platform_data);
#endif
s5p_fimd1_set_platdata(&universal5410_lcd1_pdata);
#ifdef CONFIG_FB_S5P_EXTDSP
s3cfb_extdsp_set_platdata(&default_extdsp_data);
#endif
platform_add_devices(universal5410_display_devices,
ARRAY_SIZE(universal5410_display_devices));
#ifdef CONFIG_FB_MIPI_DSIM
#if defined(CONFIG_LCD_MIPI_S6E8FA0) || defined(CONFIG_LCD_MIPI_S6E3FA0)
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mpll_bpll", 134 * MHZ);
#endif
#endif
#ifdef CONFIG_FB_S5P_MDNIE
keep_lcd_clk(&s5p_device_fimd1.dev);
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_mdnie", "mout_mpll_bpll", 134 * MHZ);
mdnie_device_register();
#endif
#if defined(CONFIG_FB_LCD_FREQ_SWITCH)
lcdfreq_device_register();
#endif
res = platform_get_resource(&s5p_device_fimd1, IORESOURCE_MEM, 1);
if (res) {
res->start = bootloaderfb_start;
res->end = res->start + bootloaderfb_size - 1;
pr_info("bootloader fb located at %8X-%8X\n", res->start, res->end);
} else {
pr_err("failed to find bootloader fb resource\n");
}
}
static int __init restore_lcd_clk_late_init(void)
{
keep_lcd_clk(&s5p_device_fimd1.dev, 0);
return 0;
}
void __init exynos5_universal5420_display_init(void)
{
struct resource *res;
struct clk *mout_mdnie1;
struct clk *mout_mpll;
#ifdef CONFIG_FB_MIPI_DSIM
s5p_dsim1_set_platdata(&dsim_platform_data);
#endif
#ifdef CONFIG_S5P_DP
s5p_dp_set_platdata(&universal5420_dp_data);
#endif
s5p_fimd1_set_platdata(&universal5420_lcd1_pdata);
#ifdef CONFIG_BACKLIGHT_PWM
samsung_bl_set(&universal5420_bl_gpio_info, &smdk5420_bl_data);
#endif
platform_add_devices(universal5420_display_devices,
ARRAY_SIZE(universal5420_display_devices));
#ifdef CONFIG_S5P_DP
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mpll_bpll", 267 * MHZ);
#endif
mout_mdnie1 = clk_get(NULL, "mout_mdnie1");
if ((IS_ERR(mout_mdnie1)))
pr_err("Can't get clock[%s]\n", "mout_mdnie1");
mout_mpll = clk_get(NULL, "mout_mpll");
if ((IS_ERR(mout_mpll)))
pr_err("Can't get clock[%s]\n", "mout_mpll");
if (mout_mdnie1 && mout_mpll)
clk_set_parent(mout_mdnie1, mout_mpll);
if (mout_mdnie1)
clk_put(mout_mdnie1);
if (mout_mpll)
clk_put(mout_mpll);
#ifdef CONFIG_FB_MIPI_DSIM
#if defined(CONFIG_LCD_MIPI_S6E8FA0) || defined(CONFIG_LCD_MIPI_S6E3FA0)
#if defined(CONFIG_FB_I80IF) && !defined(CONFIG_FB_S5P_MDNIE)
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mdnie1", 266 * MHZ);
#else
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_mdnie1", 133 * MHZ);
#endif
#else
/* RPLL rate is 300Mhz, 300/5=60Hz */
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "mout_rpll", 67 * MHZ);
#endif
#endif
#ifdef CONFIG_FB_S5P_MDNIE
keep_lcd_clk(&s5p_device_fimd1.dev);
#if defined(CONFIG_LCD_MIPI_S6E8FA0) || defined(CONFIG_LCD_MIPI_S6E3FA0)
#ifdef CONFIG_FB_I80IF
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_mdnie", "mout_mdnie1", 266 * MHZ);
#else
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_mdnie", "mout_mdnie1", 133 * MHZ);
#endif
#endif
mdnie_device_register();
#endif
res = platform_get_resource(&s5p_device_fimd1, IORESOURCE_MEM, 1);
if (res) {
res->start = bootloaderfb_start;
res->end = res->start + bootloaderfb_size - 1;
pr_info("bootloader fb located at %8X-%8X\n", res->start, res->end);
} else {
pr_err("failed to find bootloader fb resource\n");
}
}
