C++ (Cpp) l2x0_inv_all示例

示例#1

文件： cache-l2x0.c 项目： BinVul/linux2.6.32

void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
	__u32 aux;

	l2x0_base = base;

	/* disable L2X0 */
	writel(0, l2x0_base + L2X0_CTRL);

	aux = readl(l2x0_base + L2X0_AUX_CTRL);
	aux &= aux_mask;
	aux |= aux_val;
	writel(aux, l2x0_base + L2X0_AUX_CTRL);

	l2x0_inv_all();

	/* enable L2X0 */
	writel(1, l2x0_base + L2X0_CTRL);

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;

	printk(KERN_INFO "L2X0 cache controller enabled\n");
}

示例#2

文件： cache-l2x0.c 项目： 0x0f/adam-kernel

static void l2x0_enable(__u32 aux_val, __u32 aux_mask)
{
	u32 aux;

	if (l2x0_disabled)
		return;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {

		/* l2x0 controller is disabled */

		aux = readl(l2x0_base + L2X0_AUX_CTRL);
		aux &= aux_mask;
		aux |= aux_val;
		writel(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel(1, l2x0_base + L2X0_CTRL);
	}
}

示例#3

文件： cache-l2x0.c 项目： Jokymon/barebox

void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
	__u32 aux;

	l2x0_base = base;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {

		/* l2x0 controller is disabled */

		aux = readl(l2x0_base + L2X0_AUX_CTRL);
		aux &= aux_mask;
		aux |= aux_val;
		writel(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel(1, l2x0_base + L2X0_CTRL);
	}

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;
	outer_cache.disable = l2x0_disable;
}

示例#4

文件： cache-l2x0.c 项目： fread-ink/fread-kernel-k4

void l2x0_enable(void)
{
	if (!readl(l2x0_base + L2X0_CTRL)) {
		writel(l2x0_aux, l2x0_base + L2X0_AUX_CTRL);
		l2x0_inv_all();
		/* enable L2X0 */
		writel(1, l2x0_base + L2X0_CTRL);
	}
}

示例#5

文件： cache.c 项目： xristo2121/buildroot-uboot

void dcache_invalid(void)
{
#ifndef CONFIG_SYS_NO_DCACHE
    _invalidate_dcache();
#endif
#ifdef CONFIG_CACHE_L2X0
    l2x0_inv_all();
#endif
}

示例#6

文件： cache-l2x0.c 项目： ffxx68/EVBSP-Kernel

void l2x0_resume(void)
{
	if (l2x0_base != NULL) {
		if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
			/* enable L2X0 */
			l2x0_inv_all();
			writel(1, l2x0_base + L2X0_CTRL);
		}
	}
}

示例#7

文件： cache-l2x0.c 项目： Racing1/zeppelin_kernel

void l2x0_resume(int collapsed)
{
	if (collapsed) {
		/* Disable the cache */
		writel(0, l2x0_base + L2X0_CTRL);

		/* Restore aux control register value */
		writel(aux_ctrl_save, l2x0_base + L2X0_AUX_CTRL);

		/* Invalidate the cache */
		l2x0_inv_all();
	}

	/* Enable the cache */
	writel(1, l2x0_base + L2X0_CTRL);
}

示例#8

void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
    __u32 bits;

    l2x0_base = base;

    /* disable L2X0 */
//	bits = readl(l2x0_base + L2X0_CTRL);
//	bits &= ~0x01;	/* clear bit 0 */
//	writel(bits, l2x0_base + L2X0_CTRL);

    l2x0_cache_sync();
    printk("L2X0 cache_sync\n");
    l2x0_cache_flush_all();
    printk("L2X0 cache_flush_all\n");
    writel(0, l2x0_base + L2X0_CTRL);

    bits = readl(l2x0_base + L2X0_AUX_CTRL);
    bits &= aux_mask;
    bits |= aux_val;
    writel(bits, l2x0_base + L2X0_AUX_CTRL);

    l2x0_inv_all();

    /* enable L2X0 */
    bits = readl(l2x0_base + L2X0_CTRL);
    bits |= 0x01;	/* set bit 0 */
    writel(bits, l2x0_base + L2X0_CTRL);

    bits = readl(l2x0_base + L2X0_CACHE_ID);
    bits >>= 6;	/* part no, bit 6 to 9 */
    bits &= 0x0f;	/* 4 bits */

    if (bits == 2) {	/* L220 */
        outer_cache.inv_range = l2x0_inv_range;
        outer_cache.clean_range = l2x0_clean_range;
        outer_cache.flush_range = l2x0_flush_range;
        printk(KERN_INFO "L220 cache controller enabled\n");
    } else {		/* L210 */
        outer_cache.inv_range = l2x0_inv_range_atomic;
        outer_cache.clean_range = l2x0_clean_range_atomic;
        outer_cache.flush_range = l2x0_flush_range_atomic;
        printk(KERN_INFO "L210 cache controller enabled\n");
    }

}

示例#9

文件： cache-l2x0.c 项目： ffxx68/EVBSP-Kernel

void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
	__u32 aux;

	if (l2x0_disabled) {
		printk(KERN_INFO "L2X0 cache controller disabled\n");
		return;
	}

	l2x0_base = base;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
		/* l2x0 controller is disabled */
		aux = readl(l2x0_base + L2X0_AUX_CTRL);
		aux &= aux_mask;
		aux |= aux_val;
		writel(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel(1, l2x0_base + L2X0_CTRL);
	}

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;
	outer_cache.flush_all = l2x0_flush_all;
	outer_cache.sync = l2x0_cache_sync;

	pr_info(L2CC_TYPE " cache controller enabled\n");
}

示例#10

文件： translation.c 项目： codesnake/uboot-amlogic

void l2x0_enable()
{
	unsigned aux;
	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl( L2X0_CTRL) & 1)) {

		/* l2x0 controller is disabled */

		aux = readl(L2X0_AUX_CTRL);
		aux &= 0xff800fff;
		aux |= 0x00020000;
		writel(aux,L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel(1,  L2X0_CTRL);
	}

}

示例#11

文件： cache-l310.c 项目： Antares84/asuswrt-merlin

void __init l310_init(void __iomem *base, u32 aux_val, u32 aux_mask, int irq)
{
	__u32 aux;
	__u32 cache_id;
	int ways;

	l2x0_base = base;
	l2x0_irq = irq;

	cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);

	aux &= aux_mask;
	aux |= aux_val;

	/* This module unly supports the L310 */
	BUG_ON((cache_id & L2X0_CACHE_ID_PART_MASK) != L2X0_CACHE_ID_PART_L310);

	/* Determine the number of ways */
	if (aux & (1 << 16))
		ways = 16;
	else
		ways = 8;

	l2x0_way_mask = (1 << ways) - 1;

	/*
	 * Check if l2x0 controller is already enabled.
	 * If you are booting from non-secure mode
	 * accessing the below registers will fault.
	 */
	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {

		/* l2x0 controller is disabled */
		writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);

		l2x0_inv_all();

		/* enable L2X0 */
		writel_relaxed(1, l2x0_base + L2X0_CTRL);
	}

 	/* Enable interrupts */
 	WARN_ON( request_irq( l2x0_irq, l2x0_isr, 0, "L2C", NULL ));
 	writel_relaxed(0x00ff, l2x0_base + L2X0_INTR_MASK);

	outer_cache.inv_range = l2x0_inv_range;
	outer_cache.clean_range = l2x0_clean_range;
	outer_cache.flush_range = l2x0_flush_range;
	outer_cache.sync = l2x0_cache_sync;

	/* configure total hits */
	writel_relaxed((2 << 2), l2x0_base + L2X0_EVENT_CNT1_CFG);

	/* configure total read accesses */
	writel_relaxed((3 << 2), l2x0_base + L2X0_EVENT_CNT0_CFG);

	/* enable event counting */
	writel_relaxed(0x1, l2x0_base + L2X0_EVENT_CNT_CTRL);

	printk(KERN_INFO "L310: cache controller enabled %d ways, "
			"CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
			 ways, cache_id, aux);
}