static void rk3188_lcdc_deint(struct rk3188_lcdc_device * lcdc_dev)
{
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_dev->clk_on = 0;
lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, v_FS_INT_CLEAR(1));
lcdc_msk_reg(lcdc_dev, INT_STATUS, m_HS_INT_EN | m_FS_INT_EN |
m_LF_INT_EN | m_BUS_ERR_INT_EN,v_HS_INT_EN(0) | v_FS_INT_EN(0) |
v_LF_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt
lcdc_set_bit(lcdc_dev,SYS_CTRL,m_LCDC_STANDBY);
lcdc_cfg_done(lcdc_dev);
spin_unlock(&lcdc_dev->reg_lock);
}
else //clk already disabled
{
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
mdelay(1);
}
static int rk3188_lcdc_init(struct rk_lcdc_device_driver *dev_drv)
{
int i = 0;
int __iomem *c;
int v;
struct rk3188_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3188_lcdc_device,driver);
if(lcdc_dev->id == 0) //lcdc0
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0");
}
else if(lcdc_dev->id == 1)
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1");
}
else
{
printk(KERN_ERR "invalid lcdc device!\n");
return -EINVAL;
}
if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk)))
{
printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id);
}
rk3188_lcdc_clk_enable(lcdc_dev);
if(lcdc_dev->id == 0)
{
#if defined(CONFIG_LCDC0_IO_18V)
v = 0x40004000; //bit14: 1,1.8v;0,3.3v
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#else
v = 0x40000000;
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#endif
}
if(lcdc_dev->id == 1) //iomux for lcdc1
{
#if defined(CONFIG_LCDC1_IO_18V)
v = 0x80008000; //bit14: 1,1.8v;0,3.3v
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#else
v = 0x80000000;
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#endif
iomux_set(LCDC1_DCLK);
iomux_set(LCDC1_DEN);
iomux_set(LCDC1_HSYNC);
iomux_set(LCDC1_VSYNC);
iomux_set(LCDC1_D0);
iomux_set(LCDC1_D1);
iomux_set(LCDC1_D2);
iomux_set(LCDC1_D3);
iomux_set(LCDC1_D4);
iomux_set(LCDC1_D5);
iomux_set(LCDC1_D6);
iomux_set(LCDC1_D7);
iomux_set(LCDC1_D8);
iomux_set(LCDC1_D9);
iomux_set(LCDC1_D10);
iomux_set(LCDC1_D11);
iomux_set(LCDC1_D12);
iomux_set(LCDC1_D13);
iomux_set(LCDC1_D14);
iomux_set(LCDC1_D15);
iomux_set(LCDC1_D16);
iomux_set(LCDC1_D17);
iomux_set(LCDC1_D18);
iomux_set(LCDC1_D19);
iomux_set(LCDC1_D20);
iomux_set(LCDC1_D21);
iomux_set(LCDC1_D22);
iomux_set(LCDC1_D23);
}
lcdc_set_bit(lcdc_dev,SYS_CTRL,m_AUTO_GATING_EN);//eanble axi-clk auto gating for low power
//lcdc_set_bit(lcdc_dev,DSP_CTRL0,m_WIN0_TOP);
if(dev_drv->cur_screen->dsp_lut)
{
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
lcdc_cfg_done(lcdc_dev);
msleep(25);
for(i=0;i<256;i++)
{
v = dev_drv->cur_screen->dsp_lut[i];
c = lcdc_dev->dsp_lut_addr_base+i;
writel_relaxed(v,c);
}
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));
}
lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective
rk3188_lcdc_clk_disable(lcdc_dev);
return 0;
}
static int rk30_lcdc_init(struct rk_lcdc_device_driver *dev_drv)
{
int i = 0;
int __iomem *c;
int v;
struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver);
if(lcdc_dev->id == 0) //lcdc0
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0");
}
else if(lcdc_dev->id == 1)
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1");
}
else
{
printk(KERN_ERR "invalid lcdc device!\n");
return -EINVAL;
}
if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk)))
{
printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id);
}
rk30_lcdc_clk_enable(lcdc_dev);
rk30_lcdc_read_reg_defalut_cfg(lcdc_dev);
lcdc_msk_reg(lcdc_dev,SYS_CTRL0,m_HWC_CHANNEL_ID | m_WIN2_CHANNEL_ID | m_WIN1_CBR_CHANNEL_ID |
m_WIN1_YRGB_CHANNEL_ID | m_WIN0_CBR_CHANNEL1_ID | m_WIN0_YRGB_CHANNEL1_ID |
m_WIN0_CBR_CHANNEL0_ID | m_WIN0_YRGB_CHANNEL0_ID,v_HWC_CHANNEL_ID(7) |
v_WIN2_CHANNEL_ID(6) | v_WIN1_CBR_CHANNEL_ID(5) | v_WIN1_YRGB_CHANNEL_ID(4) |
v_WIN0_CBR_CHANNEL1_ID(3) | v_WIN0_YRGB_CHANNEL1_ID(2) | v_WIN0_CBR_CHANNEL0_ID(1) |
v_WIN0_YRGB_CHANNEL0_ID(0)); //channel id ,just use default value
lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_YRGB,0x10001000);
lcdc_writel(lcdc_dev,WIN1_SCL_FACTOR_YRGB,0x10001000);
lcdc_set_bit(lcdc_dev,DSP_CTRL0, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power
lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN |
m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) |
v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync
if(dev_drv->cur_screen->dsp_lut)
{
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0));
lcdc_cfg_done(lcdc_dev);
msleep(25);
for(i=0;i<256;i++)
{
v = dev_drv->cur_screen->dsp_lut[i];
c = lcdc_dev->dsp_lut_addr_base+i;
writel_relaxed(v,c);
}
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1));
}
lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective
rk30_lcdc_clk_disable(lcdc_dev);
return 0;
}
