/*--------------------------------------------------------------------------------------------- * (function: activity_estimation) *-------------------------------------------------------------------------------------------*/ void activity_estimation(char *input_filename, char *output_filename, int lut_size, netlist_t *LUT_netlist, netlist_t *CLUSTER_netlist) { /* levelize the graph. Note, can't levelize the ClUSTER_netlist since there are loops */ levelize_and_check_for_combinational_loop_and_liveness(FALSE, LUT_netlist); /* initializes the data structures and the PI */ initialize_probabilities(input_filename, LUT_netlist); /* Calculate the probabilities for each of the nodes in the LUT_netlist */ calc_probabilities_and_init_act_data(LUT_netlist); /* calculate the transition density for each node */ calc_transition_density(LUT_netlist); /* Output file with the transition densities */ output_activation_file_ace_and_function_file(output_filename, lut_size, LUT_netlist, CLUSTER_netlist); /* cleanup the data structures so we can use node_data in another algorithm */ cleanup_activation(LUT_netlist); /* Path is where we are */ // graphVizOutputNetlist(configuration.debug_output_path, "blif", 1, blif_gnd_node, blif_vcc_node, blif_input_nodes, num_blif_input_nodes); }
/*--------------------------------------------------------------------------- * (function: do_high_level_synthesis) *-------------------------------------------------------------------------*/ void do_high_level_synthesis() { double elaboration_time = wall_time(); printf("--------------------------------------------------------------------\n"); printf("High-level synthesis Begin\n"); /* Perform any initialization routines here */ #ifdef VPR6 find_hard_multipliers(); find_hard_adders(); //find_hard_adders_for_sub(); register_hard_blocks(); #endif global_param_table_sc = sc_new_string_cache(); /* parse to abstract syntax tree */ printf("Parser starting - we'll create an abstract syntax tree. " "Note this tree can be viewed using GraphViz (see documentation)\n"); parse_to_ast(); /* Note that the entry point for ast optimzations is done per module with the * function void next_parsed_verilog_file(ast_node_t *file_items_list) */ /* after the ast is made potentiatlly do tagging for downstream links to verilog */ if (global_args.high_level_block != NULL) { add_tag_data(); } /* Now that we have a parse tree (abstract syntax tree [ast]) of * the Verilog we want to make into a netlist. */ printf("Converting AST into a Netlist. " "Note this netlist can be viewed using GraphViz (see documentation)\n"); create_netlist(); // Can't levelize yet since the large muxes can look like combinational loops when they're not check_netlist(verilog_netlist); /* point for all netlist optimizations. */ printf("Performing Optimizations of the Netlist\n"); netlist_optimizations_top(verilog_netlist); if (configuration.output_netlist_graphs ) { /* Path is where we are */ graphVizOutputNetlist(configuration.debug_output_path, "optimized", 1, verilog_netlist); } /* point where we convert netlist to FPGA or other hardware target compatible format */ printf("Performing Partial Map to target device\n"); partial_map_top(verilog_netlist); #ifdef VPR5 /* check for problems in the partial mapped netlist */ printf("Check for liveness and combinational loops\n"); levelize_and_check_for_combinational_loop_and_liveness(TRUE, verilog_netlist); #endif /* point for outputs. This includes soft and hard mapping all structures to the * target format. Some of these could be considred optimizations */ printf("Outputting the netlist to the specified output format\n"); output_top(verilog_netlist); elaboration_time = wall_time() - elaboration_time; printf("Successful High-level synthesis by Odin in "); print_time(elaboration_time); printf("\n"); printf("--------------------------------------------------------------------\n"); // FIXME: free contents? sc_free_string_cache(global_param_table_sc); }