static void lio_cn23xx_pf_bar1_idx_setup(struct octeon_device *oct, uint64_t core_addr, uint32_t idx, int valid) { volatile uint64_t bar1; uint64_t reg_adr; if (!valid) { reg_adr = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); bar1 = reg_adr; lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL), LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); reg_adr = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); bar1 = reg_adr; return; } /* * The PEM(0..3)_BAR1_INDEX(0..15)[ADDR_IDX]<23:4> stores * bits <41:22> of the Core Addr */ lio_pci_writeq(oct, (((core_addr >> 22) << 4) | LIO_PCI_BAR1_MASK), LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); bar1 = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); }
static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct) { u32 i; u32 fifo_sizes[6] = { 3, 3, 1, 1, 1, 8 }; lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL); dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n", lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL)); for (i = 0; i < 6; i++) { /* Prevent service of instruction queue for all DMA engines * Engine 5 will remain 0. Engines 0 - 4 will be setup by * core. */ lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i)); lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i)); dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i, lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i))); } /* DPI_SLI_PRT_CFG has MPS and MRRS settings that will be set * separately. */ lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL); dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n", lio_pci_readq(oct, CN6XXX_DPI_CTL)); }
int lio_cn6xxx_soft_reset(struct octeon_device *oct) { octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF); dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n"); lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_BIST); octeon_write_csr64(oct, CN6XXX_SLI_SCRATCH1, 0x1234ULL); lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST); lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_RST); /* make sure that the reset is written before starting timer */ mmiowb(); /* Wait for 10ms as Octeon resets. */ mdelay(100); if (octeon_read_csr64(oct, CN6XXX_SLI_SCRATCH1) == 0x1234ULL) { dev_err(&oct->pci_dev->dev, "Soft reset failed\n"); return 1; } dev_dbg(&oct->pci_dev->dev, "Reset completed\n"); octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF); return 0; }
static int lio_cn23xx_pf_soft_reset(struct octeon_device *oct) { lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF); lio_dev_dbg(oct, "BIST enabled for CN23XX soft reset\n"); lio_write_csr64(oct, LIO_CN23XX_SLI_SCRATCH1, 0x1234ULL); /* Initiate chip-wide soft reset */ lio_pci_readq(oct, LIO_CN23XX_RST_SOFT_RST); lio_pci_writeq(oct, 1, LIO_CN23XX_RST_SOFT_RST); /* Wait for 100ms as Octeon resets. */ lio_mdelay(100); if (lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH1)) { lio_dev_err(oct, "Soft reset failed\n"); return (1); } lio_dev_dbg(oct, "Reset completed\n"); /* restore the reset value */ lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF); return (0); }
static uint32_t lio_cn23xx_pf_bar1_idx_read(struct octeon_device *oct, uint32_t idx) { return ((uint32_t)lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx))); }
static int lio_is_210nv(struct octeon_device *oct) { u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG); return ((mio_qlm4_cfg & CN6XXX_MIO_QLM_CFG_MASK) == 0); }
static int cn6xxx_read_csr_reg(char *s, struct octeon_device *oct) { u32 reg; int i, len = 0; /* PCI Window Registers */ len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n"); reg = CN6XXX_WIN_WR_ADDR_LO; len += sprintf(s + len, "\n[%02x] (WIN_WR_ADDR_LO): %08x\n", CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg)); reg = CN6XXX_WIN_WR_ADDR_HI; len += sprintf(s + len, "[%02x] (WIN_WR_ADDR_HI): %08x\n", CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg)); reg = CN6XXX_WIN_RD_ADDR_LO; len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_LO): %08x\n", CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg)); reg = CN6XXX_WIN_RD_ADDR_HI; len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_HI): %08x\n", CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg)); reg = CN6XXX_WIN_WR_DATA_LO; len += sprintf(s + len, "[%02x] (WIN_WR_DATA_LO): %08x\n", CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg)); reg = CN6XXX_WIN_WR_DATA_HI; len += sprintf(s + len, "[%02x] (WIN_WR_DATA_HI): %08x\n", CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg)); len += sprintf(s + len, "[%02x] (WIN_WR_MASK_REG): %08x\n", CN6XXX_WIN_WR_MASK_REG, octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG)); /* PCI Interrupt Register */ len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n", CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT0)); len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 1): %08x\n", CN6XXX_SLI_INT_ENB64_PORT1, octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1)); len += sprintf(s + len, "[%x] (INT_SUM): %08x\n", CN6XXX_SLI_INT_SUM64, octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64)); /* PCI Output queue registers */ for (i = 0; i < oct->num_oqs; i++) { reg = CN6XXX_SLI_OQ_PKTS_SENT(i); len += sprintf(s + len, "\n[%x] (PKTS_SENT_%d): %08x\n", reg, i, octeon_read_csr(oct, reg)); reg = CN6XXX_SLI_OQ_PKTS_CREDIT(i); len += sprintf(s + len, "[%x] (PKT_CREDITS_%d): %08x\n", reg, i, octeon_read_csr(oct, reg)); } reg = CN6XXX_SLI_OQ_INT_LEVEL_PKTS; len += sprintf(s + len, "\n[%x] (PKTS_SENT_INT_LEVEL): %08x\n", reg, octeon_read_csr(oct, reg)); reg = CN6XXX_SLI_OQ_INT_LEVEL_TIME; len += sprintf(s + len, "[%x] (PKTS_SENT_TIME): %08x\n", reg, octeon_read_csr(oct, reg)); /* PCI Input queue registers */ for (i = 0; i <= 3; i++) { u32 reg; reg = CN6XXX_SLI_IQ_DOORBELL(i); len += sprintf(s + len, "\n[%x] (INSTR_DOORBELL_%d): %08x\n", reg, i, octeon_read_csr(oct, reg)); reg = CN6XXX_SLI_IQ_INSTR_COUNT(i); len += sprintf(s + len, "[%x] (INSTR_COUNT_%d): %08x\n", reg, i, octeon_read_csr(oct, reg)); } /* PCI DMA registers */ len += sprintf(s + len, "\n[%x] (DMA_CNT_0): %08x\n", CN6XXX_DMA_CNT(0), octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); reg = CN6XXX_DMA_PKT_INT_LEVEL(0); len += sprintf(s + len, "[%x] (DMA_INT_LEV_0): %08x\n", CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); reg = CN6XXX_DMA_TIME_INT_LEVEL(0); len += sprintf(s + len, "[%x] (DMA_TIME_0): %08x\n", CN6XXX_DMA_TIME_INT_LEVEL(0), octeon_read_csr(oct, reg)); len += sprintf(s + len, "\n[%x] (DMA_CNT_1): %08x\n", CN6XXX_DMA_CNT(1), octeon_read_csr(oct, CN6XXX_DMA_CNT(1))); reg = CN6XXX_DMA_PKT_INT_LEVEL(1); len += sprintf(s + len, "[%x] (DMA_INT_LEV_1): %08x\n", CN6XXX_DMA_PKT_INT_LEVEL(1), octeon_read_csr(oct, reg)); reg = CN6XXX_DMA_PKT_INT_LEVEL(1); len += sprintf(s + len, "[%x] (DMA_TIME_1): %08x\n", CN6XXX_DMA_TIME_INT_LEVEL(1), octeon_read_csr(oct, reg)); /* PCI Index registers */ len += sprintf(s + len, "\n"); for (i = 0; i < 16; i++) { reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port)); len += sprintf(s + len, "[%llx] (BAR1_INDEX_%02d): %08x\n", CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg); } return len; }