static void queue(struct vc4_compile *c, uint64_t inst) { struct queued_qpu_inst *q = rzalloc(c, struct queued_qpu_inst); q->inst = inst; list_addtail(&q->link, &c->qpu_inst_list); }
void fd_bo_del(struct fd_bo *bo) { struct fd_device *dev = bo->dev; if (!atomic_dec_and_test(&bo->refcnt)) return; pthread_mutex_lock(&table_lock); if (bo->bo_reuse) { struct fd_bo_bucket *bucket = get_bucket(dev, bo->size); /* see if we can be green and recycle: */ if (bucket) { struct timespec time; clock_gettime(CLOCK_MONOTONIC, &time); bo->free_time = time.tv_sec; list_addtail(&bo->list, &bucket->list); fd_cleanup_bo_cache(dev, time.tv_sec); /* bo's in the bucket cache don't have a ref and * don't hold a ref to the dev: */ goto out; } } bo_del(bo); out: fd_device_del_locked(dev); pthread_mutex_unlock(&table_lock); }
//添加学生的函数 void addstudent() { struct student stu; int flag; while(1) { flag = 0; CLEAR_SCREEN(); struct list *find; printf("\033[33m\033[2;50H%s\033[0m","请输入以下信息"); printf("\033[33m\033[4;50H%s\033[0m","请输入学生的ID:"); scanf("%s",stu.id); find = list_find(list_student, &stu, comp_id_stu); if(find != NULL) { printf("\033[33m\033[6;50H%s\033[0m","帐号已注册,请按任意键重试。\n"); getchar(); getchar(); } else { flag = 1; } if(flag == 1) { break; } } printf("\033[33m\033[5;50H%s\033[0m","请输入学生的密码:"); scanf("%s",stu.pass); printf("\033[33m\033[6;50H%s\033[0m","请输入学生的姓名:"); scanf("%s",stu.name); printf("\033[33m\033[7;50H%s\033[0m","请输入学生的年龄:"); scanf("%d",&stu.age); printf("\033[33m\033[8;50H%s\033[0m","请输入学生的班级:"); scanf("%s",stu.class); printf("\033[33m\033[9;50H%s\033[0m","请输入学生的语文成绩:"); scanf("%d",&stu.grade[0]); printf("\033[33m\033[10;50H%s\033[0m","请输入学生的数学成绩:"); scanf("%d",&stu.grade[1]); printf("\033[33m\033[11;50H%s\033[0m","请输入学生的C语言成绩:"); scanf("%d",&stu.grade[2]); stu.average = (stu.grade[0]+stu.grade[1]+stu.grade[2])/3; //将stu插到链表中去 if(list_addtail(list_student,&stu) == 0) { printf("\033[33m\033[12;50H%s\033[0m","添加学生数据成功!\n"); getchar(); getchar(); } else { printf("\033[33m\033[12;50H%s\033[0m","添加学生数据失败!\n"); getchar(); getchar(); } }
void ppir_node_add_dep(ppir_node *succ, ppir_node *pred) { /* don't add dep for two nodes from different block */ if (succ->block != pred->block) return; /* don't add duplicated dep */ ppir_node_foreach_pred(succ, dep) { if (dep->pred == pred) return; } ppir_dep *dep = ralloc(succ, ppir_dep); dep->pred = pred; dep->succ = succ; list_addtail(&dep->pred_link, &succ->pred_list); list_addtail(&dep->succ_link, &pred->succ_list); }
static void pause_query(struct fd_context *ctx, struct fd_hw_query *hq, struct fd_ringbuffer *ring) { int idx = pidx(hq->provider->query_type); assert(idx >= 0); /* query never would have been created otherwise */ assert(hq->period && !hq->period->end); assert(ctx->active_providers & (1 << idx)); hq->period->end = get_sample(ctx, ring, hq->base.type); list_addtail(&hq->period->list, &hq->current_periods); hq->period = NULL; }
void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list) { /* remove from existing spot in list: */ list_delinit(&instr->node); /* find where to re-insert instruction: */ list_for_each_entry (struct ir3_instruction, pos, list, node) { if (pos->depth > instr->depth) { list_add(&instr->node, &pos->node); return; } } /* if we get here, we didn't find an insertion spot: */ list_addtail(&instr->node, list); }
struct reloc_worklist_entry * clif_dump_add_address_to_worklist(struct clif_dump *clif, enum reloc_worklist_type type, uint32_t addr) { struct reloc_worklist_entry *entry = rzalloc(clif, struct reloc_worklist_entry); if (!entry) return NULL; entry->type = type; entry->addr = addr; list_addtail(&entry->link, &clif->worklist); return entry; }
static void create_object(const char *chipname, const char *featurename, const sensors_chip_name *chip, const sensors_feature *feature, int mode) { struct sensors_temp_info *sti = CALLOC_STRUCT(sensors_temp_info); sti->mode = mode; sti->chip = (sensors_chip_name *) chip; sti->feature = feature; strcpy(sti->chipname, chipname); strcpy(sti->featurename, featurename); snprintf(sti->name, sizeof(sti->name), "%s.%s", sti->chipname, sti->featurename); list_addtail(&sti->list, &gsensors_temp_list); gsensors_temp_count++; }
void etna_resource_used(struct etna_context *ctx, struct pipe_resource *prsc, enum etna_resource_status status) { struct etna_resource *rsc; if (!prsc) return; rsc = etna_resource(prsc); rsc->status |= status; /* TODO resources can actually be shared across contexts, * so I'm not sure a single list-head will do the trick? */ debug_assert((rsc->pending_ctx == ctx) || !rsc->pending_ctx); list_delinit(&rsc->list); list_addtail(&rsc->list, &ctx->used_resources); rsc->pending_ctx = ctx; }
static void virgl_buffer_transfer_flush_region(struct pipe_context *ctx, struct pipe_transfer *transfer, const struct pipe_box *box) { struct virgl_context *vctx = virgl_context(ctx); struct virgl_buffer *vbuf = virgl_buffer(transfer->resource); if (!vbuf->on_list) { struct pipe_resource *res = NULL; list_addtail(&vbuf->flush_list, &vctx->to_flush_bufs); vbuf->on_list = TRUE; pipe_resource_reference(&res, &vbuf->base.u.b); } util_range_add(&vbuf->valid_buffer_range, transfer->box.x + box->x, transfer->box.x + box->x + box->width); vbuf->base.clean = FALSE; }
//学生数据初始化 int init_student() { FILE *fp; struct student stu; //创建链表用于存放学生的数据 list_student = list_create(sizeof(struct student)); if(list_student == NULL) { //分配链表头结点失败 return -1; } //读取student.dat文件,然后保存所有的数据到list_student链表里面 fp = fopen("dat/student.dat","r"); if(fp == NULL) { // printf("没有student.dat文件.\n"); fp = fopen("dat/student.dat","w+"); if(fp == NULL) { list_destroy(&list_student); return -1; } } while(1) { if(fread(&stu, sizeof(stu), 1, fp) != 1) { //读取文件结束 if(feof(fp) || ferror(fp)) { break; } } if(list_addtail(list_student, &stu) == -1) { list_destroy(&list_student); fclose(fp); return -1; } } fclose(fp); return 0; }
//管理员初始化 int init_manager() { FILE *fp; struct manager man = {"admin" , "admin"}; //创建一个链表用于存放管理员的数据 list_manager = list_create(sizeof(struct manager)); if(list_manager == NULL) { return -1; } //读取manager.dat文件,然后保存所有的数据到链表里面 fp = fopen("dat/manager.dat","r"); if(fp == NULL) //文件不存在 { fp = fopen("dat/manager.dat", "w+"); //创建该文件 if(fp == NULL) { list_destroy(&list_manager); return -1; } fwrite(&man, sizeof(man), 1, fp); rewind(fp); } while(1) { if(fread(&man, sizeof(man), 1, fp) != 1) { //读取文件结束 if(feof(fp) || ferror(fp)) break; } //把man的信息写道链表里面 if(list_addtail(list_manager, &man) == -1) { list_destroy(&list_manager); fclose(fp); return -1; } } fclose(fp); return 0; }
static struct vc4_mem_area_rec * vc4_add_mem_area_to_list(struct vc4_mem_area_rec *rec) { /* Don't add exact duplicates of memory areas to the list. We have to * be careful to not compare the list pointers, since the new rec * won't be in the list. */ struct vc4_mem_area_rec compare_a = *rec; memset(&compare_a.link, 0, sizeof(compare_a.link)); list_for_each_entry(struct vc4_mem_area_rec, list_rec, &dump.mem_areas, link) { struct vc4_mem_area_rec compare_b = *list_rec; memset(&compare_b.link, 0, sizeof(compare_b.link)); if (memcmp(&compare_a, &compare_b, sizeof(compare_a)) == 0) return list_rec; } struct vc4_mem_area_rec *list_rec = malloc(sizeof(*list_rec)); *list_rec = *rec; list_addtail(&list_rec->link, &dump.mem_areas); return list_rec; }
static void schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr) { debug_assert(ctx->block == instr->block); /* maybe there is a better way to handle this than just stuffing * a nop.. ideally we'd know about this constraint in the * scheduling and depth calculation.. */ if (ctx->scheduled && is_sfu_or_mem(ctx->scheduled) && is_sfu_or_mem(instr)) ir3_NOP(ctx->block); /* remove from depth list: */ list_delinit(&instr->node); if (writes_addr(instr)) { debug_assert(ctx->addr == NULL); ctx->addr = instr; } if (writes_pred(instr)) { debug_assert(ctx->pred == NULL); ctx->pred = instr; } instr->flags |= IR3_INSTR_MARK; list_addtail(&instr->node, &instr->block->instr_list); ctx->scheduled = instr; if (writes_addr(instr) || writes_pred(instr) || is_input(instr)) { clear_cache(ctx, NULL); } else { /* invalidate only the necessary entries.. */ clear_cache(ctx, instr); } }
static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, struct vc4_rcl_setup *setup) { struct drm_vc4_submit_cl *args = exec->args; bool has_bin = args->bin_cl_size != 0; uint8_t min_x_tile = args->min_x_tile; uint8_t min_y_tile = args->min_y_tile; uint8_t max_x_tile = args->max_x_tile; uint8_t max_y_tile = args->max_y_tile; uint8_t xtiles = max_x_tile - min_x_tile + 1; uint8_t ytiles = max_y_tile - min_y_tile + 1; uint8_t x, y; uint32_t size, loop_body_size; size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE; loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE; if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { size += VC4_PACKET_CLEAR_COLORS_SIZE + VC4_PACKET_TILE_COORDINATES_SIZE + VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; } if (setup->color_read) { if (args->color_read.flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; } else { loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; } } if (setup->zs_read) { if (args->zs_read.flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; } else { if (setup->color_read && !(args->color_read.flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) { loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; } loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; } } if (has_bin) { size += VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE; loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE; } if (setup->msaa_color_write) loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; if (setup->msaa_zs_write) loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; if (setup->zs_write) loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; if (setup->color_write) loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE; /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */ loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE * ((setup->msaa_color_write != NULL) + (setup->msaa_zs_write != NULL) + (setup->color_write != NULL) + (setup->zs_write != NULL) - 1); size += xtiles * ytiles * loop_body_size; setup->rcl = drm_gem_cma_create(dev, size); if (!setup->rcl) return -ENOMEM; list_addtail(&to_vc4_bo(&setup->rcl->base)->unref_head, &exec->unref_list); rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG); rcl_u32(setup, (setup->color_write ? (setup->color_write->paddr + args->color_write.offset) : 0)); rcl_u16(setup, args->width); rcl_u16(setup, args->height); rcl_u16(setup, args->color_write.bits); /* The tile buffer gets cleared when the previous tile is stored. If * the clear values changed between frames, then the tile buffer has * stale clear values in it, so we have to do a store in None mode (no * writes) so that we trigger the tile buffer clear. */ if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { rcl_u8(setup, VC4_PACKET_CLEAR_COLORS); rcl_u32(setup, args->clear_color[0]); rcl_u32(setup, args->clear_color[1]); rcl_u32(setup, args->clear_z); rcl_u8(setup, args->clear_s); vc4_tile_coordinates(setup, 0, 0); rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE); rcl_u32(setup, 0); /* no address, since we're in None mode */ } for (y = min_y_tile; y <= max_y_tile; y++) { for (x = min_x_tile; x <= max_x_tile; x++) { bool first = (x == min_x_tile && y == min_y_tile); bool last = (x == max_x_tile && y == max_y_tile); emit_tile(exec, setup, x, y, first, last); } } BUG_ON(setup->next_offset != size); exec->ct1ca = setup->rcl->paddr; exec->ct1ea = setup->rcl->paddr + setup->next_offset; return 0; }
int iris_bo_busy(struct iris_bo *bo) { struct iris_bufmgr *bufmgr = bo->bufmgr; struct drm_i915_gem_busy busy = { .handle = bo->gem_handle }; int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_BUSY, &busy); if (ret == 0) { bo->idle = !busy.busy; return busy.busy; } return false; } int iris_bo_madvise(struct iris_bo *bo, int state) { struct drm_i915_gem_madvise madv = { .handle = bo->gem_handle, .madv = state, .retained = 1, }; drm_ioctl(bo->bufmgr->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv); return madv.retained; } /* drop the oldest entries that have been purged by the kernel */ static void iris_bo_cache_purge_bucket(struct iris_bufmgr *bufmgr, struct bo_cache_bucket *bucket) { list_for_each_entry_safe(struct iris_bo, bo, &bucket->head, head) { if (iris_bo_madvise(bo, I915_MADV_DONTNEED)) break; list_del(&bo->head); bo_free(bo); } } static struct iris_bo * bo_calloc(void) { struct iris_bo *bo = calloc(1, sizeof(*bo)); if (bo) { bo->hash = _mesa_hash_pointer(bo); } return bo; } static struct iris_bo * bo_alloc_internal(struct iris_bufmgr *bufmgr, const char *name, uint64_t size, enum iris_memory_zone memzone, unsigned flags, uint32_t tiling_mode, uint32_t stride) { struct iris_bo *bo; unsigned int page_size = getpagesize(); int ret; struct bo_cache_bucket *bucket; bool alloc_from_cache; uint64_t bo_size; bool zeroed = false; if (flags & BO_ALLOC_ZEROED) zeroed = true; if ((flags & BO_ALLOC_COHERENT) && !bufmgr->has_llc) { bo_size = MAX2(ALIGN(size, page_size), page_size); bucket = NULL; goto skip_cache; } /* Round the allocated size up to a power of two number of pages. */ bucket = bucket_for_size(bufmgr, size); /* If we don't have caching at this size, don't actually round the * allocation up. */ if (bucket == NULL) { bo_size = MAX2(ALIGN(size, page_size), page_size); } else { bo_size = bucket->size; } mtx_lock(&bufmgr->lock); /* Get a buffer out of the cache if available */ retry: alloc_from_cache = false; if (bucket != NULL && !list_empty(&bucket->head)) { /* If the last BO in the cache is idle, then reuse it. Otherwise, * allocate a fresh buffer to avoid stalling. */ bo = LIST_ENTRY(struct iris_bo, bucket->head.next, head); if (!iris_bo_busy(bo)) { alloc_from_cache = true; list_del(&bo->head); } if (alloc_from_cache) { if (!iris_bo_madvise(bo, I915_MADV_WILLNEED)) { bo_free(bo); iris_bo_cache_purge_bucket(bufmgr, bucket); goto retry; } if (bo_set_tiling_internal(bo, tiling_mode, stride)) { bo_free(bo); goto retry; } if (zeroed) { void *map = iris_bo_map(NULL, bo, MAP_WRITE | MAP_RAW); if (!map) { bo_free(bo); goto retry; } memset(map, 0, bo_size); } } } if (alloc_from_cache) { /* If the cached BO isn't in the right memory zone, free the old * memory and assign it a new address. */ if (memzone != iris_memzone_for_address(bo->gtt_offset)) { vma_free(bufmgr, bo->gtt_offset, bo->size); bo->gtt_offset = 0ull; } } else { skip_cache: bo = bo_calloc(); if (!bo) goto err; bo->size = bo_size; bo->idle = true; struct drm_i915_gem_create create = { .size = bo_size }; /* All new BOs we get from the kernel are zeroed, so we don't need to * worry about that here. */ ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CREATE, &create); if (ret != 0) { free(bo); goto err; } bo->gem_handle = create.handle; bo->bufmgr = bufmgr; bo->tiling_mode = I915_TILING_NONE; bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; bo->stride = 0; if (bo_set_tiling_internal(bo, tiling_mode, stride)) goto err_free; /* Calling set_domain() will allocate pages for the BO outside of the * struct mutex lock in the kernel, which is more efficient than waiting * to create them during the first execbuf that uses the BO. */ struct drm_i915_gem_set_domain sd = { .handle = bo->gem_handle, .read_domains = I915_GEM_DOMAIN_CPU, .write_domain = 0, }; if (drm_ioctl(bo->bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &sd) != 0) goto err_free; } bo->name = name; p_atomic_set(&bo->refcount, 1); bo->reusable = bucket && bufmgr->bo_reuse; bo->cache_coherent = bufmgr->has_llc; bo->index = -1; bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED; /* By default, capture all driver-internal buffers like shader kernels, * surface states, dynamic states, border colors, and so on. */ if (memzone < IRIS_MEMZONE_OTHER) bo->kflags |= EXEC_OBJECT_CAPTURE; if (bo->gtt_offset == 0ull) { bo->gtt_offset = vma_alloc(bufmgr, memzone, bo->size, 1); if (bo->gtt_offset == 0ull) goto err_free; } mtx_unlock(&bufmgr->lock); if ((flags & BO_ALLOC_COHERENT) && !bo->cache_coherent) { struct drm_i915_gem_caching arg = { .handle = bo->gem_handle, .caching = 1, }; if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg) == 0) { bo->cache_coherent = true; bo->reusable = false; } } DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo->gem_handle, bo->name, memzone_name(memzone), (unsigned long long) size); return bo; err_free: bo_free(bo); err: mtx_unlock(&bufmgr->lock); return NULL; } struct iris_bo * iris_bo_alloc(struct iris_bufmgr *bufmgr, const char *name, uint64_t size, enum iris_memory_zone memzone) { return bo_alloc_internal(bufmgr, name, size, memzone, 0, I915_TILING_NONE, 0); } struct iris_bo * iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr, const char *name, uint64_t size, enum iris_memory_zone memzone, uint32_t tiling_mode, uint32_t pitch, unsigned flags) { return bo_alloc_internal(bufmgr, name, size, memzone, flags, tiling_mode, pitch); } struct iris_bo * iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name, void *ptr, size_t size, enum iris_memory_zone memzone) { struct iris_bo *bo; bo = bo_calloc(); if (!bo) return NULL; struct drm_i915_gem_userptr arg = { .user_ptr = (uintptr_t)ptr, .user_size = size, }; if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_USERPTR, &arg)) goto err_free; bo->gem_handle = arg.handle; /* Check the buffer for validity before we try and use it in a batch */ struct drm_i915_gem_set_domain sd = { .handle = bo->gem_handle, .read_domains = I915_GEM_DOMAIN_CPU, }; if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &sd)) goto err_close; bo->name = name; bo->size = size; bo->map_cpu = ptr; bo->bufmgr = bufmgr; bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED; bo->gtt_offset = vma_alloc(bufmgr, memzone, size, 1); if (bo->gtt_offset == 0ull) goto err_close; p_atomic_set(&bo->refcount, 1); bo->userptr = true; bo->cache_coherent = true; bo->index = -1; bo->idle = true; return bo; err_close: drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_CLOSE, &bo->gem_handle); err_free: free(bo); return NULL; } /** * Returns a iris_bo wrapping the given buffer object handle. * * This can be used when one application needs to pass a buffer object * to another. */ struct iris_bo * iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr, const char *name, unsigned int handle) { struct iris_bo *bo; /* At the moment most applications only have a few named bo. * For instance, in a DRI client only the render buffers passed * between X and the client are named. And since X returns the * alternating names for the front/back buffer a linear search * provides a sufficiently fast match. */ mtx_lock(&bufmgr->lock); bo = hash_find_bo(bufmgr->name_table, handle); if (bo) { iris_bo_reference(bo); goto out; } struct drm_gem_open open_arg = { .name = handle }; int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_OPEN, &open_arg); if (ret != 0) { DBG("Couldn't reference %s handle 0x%08x: %s\n", name, handle, strerror(errno)); bo = NULL; goto out; } /* Now see if someone has used a prime handle to get this * object from the kernel before by looking through the list * again for a matching gem_handle */ bo = hash_find_bo(bufmgr->handle_table, open_arg.handle); if (bo) { iris_bo_reference(bo); goto out; } bo = bo_calloc(); if (!bo) goto out; p_atomic_set(&bo->refcount, 1); bo->size = open_arg.size; bo->gtt_offset = 0; bo->bufmgr = bufmgr; bo->gem_handle = open_arg.handle; bo->name = name; bo->global_name = handle; bo->reusable = false; bo->external = true; bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED; bo->gtt_offset = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 1); _mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo); _mesa_hash_table_insert(bufmgr->name_table, &bo->global_name, bo); struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle }; ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling); if (ret != 0) goto err_unref; bo->tiling_mode = get_tiling.tiling_mode; bo->swizzle_mode = get_tiling.swizzle_mode; /* XXX stride is unknown */ DBG("bo_create_from_handle: %d (%s)\n", handle, bo->name); out: mtx_unlock(&bufmgr->lock); return bo; err_unref: bo_free(bo); mtx_unlock(&bufmgr->lock); return NULL; } static void bo_free(struct iris_bo *bo) { struct iris_bufmgr *bufmgr = bo->bufmgr; if (bo->map_cpu && !bo->userptr) { VG_NOACCESS(bo->map_cpu, bo->size); munmap(bo->map_cpu, bo->size); } if (bo->map_wc) { VG_NOACCESS(bo->map_wc, bo->size); munmap(bo->map_wc, bo->size); } if (bo->map_gtt) { VG_NOACCESS(bo->map_gtt, bo->size); munmap(bo->map_gtt, bo->size); } if (bo->external) { struct hash_entry *entry; if (bo->global_name) { entry = _mesa_hash_table_search(bufmgr->name_table, &bo->global_name); _mesa_hash_table_remove(bufmgr->name_table, entry); } entry = _mesa_hash_table_search(bufmgr->handle_table, &bo->gem_handle); _mesa_hash_table_remove(bufmgr->handle_table, entry); } /* Close this object */ struct drm_gem_close close = { .handle = bo->gem_handle }; int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_CLOSE, &close); if (ret != 0) { DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n", bo->gem_handle, bo->name, strerror(errno)); } vma_free(bo->bufmgr, bo->gtt_offset, bo->size); free(bo); } /** Frees all cached buffers significantly older than @time. */ static void cleanup_bo_cache(struct iris_bufmgr *bufmgr, time_t time) { int i; if (bufmgr->time == time) return; for (i = 0; i < bufmgr->num_buckets; i++) { struct bo_cache_bucket *bucket = &bufmgr->cache_bucket[i]; list_for_each_entry_safe(struct iris_bo, bo, &bucket->head, head) { if (time - bo->free_time <= 1) break; list_del(&bo->head); bo_free(bo); } } bufmgr->time = time; } static void bo_unreference_final(struct iris_bo *bo, time_t time) { struct iris_bufmgr *bufmgr = bo->bufmgr; struct bo_cache_bucket *bucket; DBG("bo_unreference final: %d (%s)\n", bo->gem_handle, bo->name); bucket = NULL; if (bo->reusable) bucket = bucket_for_size(bufmgr, bo->size); /* Put the buffer into our internal cache for reuse if we can. */ if (bucket && iris_bo_madvise(bo, I915_MADV_DONTNEED)) { bo->free_time = time; bo->name = NULL; list_addtail(&bo->head, &bucket->head); } else { bo_free(bo); } } void iris_bo_unreference(struct iris_bo *bo) { if (bo == NULL) return; assert(p_atomic_read(&bo->refcount) > 0); if (atomic_add_unless(&bo->refcount, -1, 1)) { struct iris_bufmgr *bufmgr = bo->bufmgr; struct timespec time; clock_gettime(CLOCK_MONOTONIC, &time); mtx_lock(&bufmgr->lock); if (p_atomic_dec_zero(&bo->refcount)) { bo_unreference_final(bo, time.tv_sec); cleanup_bo_cache(bufmgr, time.tv_sec); } mtx_unlock(&bufmgr->lock); } } static void bo_wait_with_stall_warning(struct pipe_debug_callback *dbg, struct iris_bo *bo, const char *action) { bool busy = dbg && !bo->idle; double elapsed = unlikely(busy) ? -get_time() : 0.0; iris_bo_wait_rendering(bo); if (unlikely(busy)) { elapsed += get_time(); if (elapsed > 1e-5) /* 0.01ms */ { perf_debug(dbg, "%s a busy \"%s\" BO stalled and took %.03f ms.\n", action, bo->name, elapsed * 1000); } } } static void print_flags(unsigned flags) { if (flags & MAP_READ) DBG("READ "); if (flags & MAP_WRITE) DBG("WRITE "); if (flags & MAP_ASYNC) DBG("ASYNC "); if (flags & MAP_PERSISTENT) DBG("PERSISTENT "); if (flags & MAP_COHERENT) DBG("COHERENT "); if (flags & MAP_RAW) DBG("RAW "); DBG("\n"); } static void * iris_bo_map_cpu(struct pipe_debug_callback *dbg, struct iris_bo *bo, unsigned flags) { struct iris_bufmgr *bufmgr = bo->bufmgr; /* We disallow CPU maps for writing to non-coherent buffers, as the * CPU map can become invalidated when a batch is flushed out, which * can happen at unpredictable times. You should use WC maps instead. */ assert(bo->cache_coherent || !(flags & MAP_WRITE)); if (!bo->map_cpu) { DBG("iris_bo_map_cpu: %d (%s)\n", bo->gem_handle, bo->name); struct drm_i915_gem_mmap mmap_arg = { .handle = bo->gem_handle, .size = bo->size, }; int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg); if (ret != 0) { DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno)); return NULL; } void *map = (void *) (uintptr_t) mmap_arg.addr_ptr; VG_DEFINED(map, bo->size); if (p_atomic_cmpxchg(&bo->map_cpu, NULL, map)) { VG_NOACCESS(map, bo->size); munmap(map, bo->size); } } assert(bo->map_cpu); DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo->gem_handle, bo->name, bo->map_cpu); print_flags(flags); if (!(flags & MAP_ASYNC)) { bo_wait_with_stall_warning(dbg, bo, "CPU mapping"); } if (!bo->cache_coherent && !bo->bufmgr->has_llc) { /* If we're reusing an existing CPU mapping, the CPU caches may * contain stale data from the last time we read from that mapping. * (With the BO cache, it might even be data from a previous buffer!) * Even if it's a brand new mapping, the kernel may have zeroed the * buffer via CPU writes. * * We need to invalidate those cachelines so that we see the latest * contents, and so long as we only read from the CPU mmap we do not * need to write those cachelines back afterwards. * * On LLC, the emprical evidence suggests that writes from the GPU * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU * cachelines. (Other reads, such as the display engine, bypass the * LLC entirely requiring us to keep dirty pixels for the scanout * out of any cache.) */ gen_invalidate_range(bo->map_cpu, bo->size); } return bo->map_cpu; } static void * iris_bo_map_wc(struct pipe_debug_callback *dbg, struct iris_bo *bo, unsigned flags) { struct iris_bufmgr *bufmgr = bo->bufmgr; if (!bo->map_wc) { DBG("iris_bo_map_wc: %d (%s)\n", bo->gem_handle, bo->name); struct drm_i915_gem_mmap mmap_arg = { .handle = bo->gem_handle, .size = bo->size, .flags = I915_MMAP_WC, }; int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg); if (ret != 0) { DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno)); return NULL; } void *map = (void *) (uintptr_t) mmap_arg.addr_ptr; VG_DEFINED(map, bo->size); if (p_atomic_cmpxchg(&bo->map_wc, NULL, map)) { VG_NOACCESS(map, bo->size); munmap(map, bo->size); } } assert(bo->map_wc); DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo->gem_handle, bo->name, bo->map_wc); print_flags(flags); if (!(flags & MAP_ASYNC)) { bo_wait_with_stall_warning(dbg, bo, "WC mapping"); } return bo->map_wc; } /** * Perform an uncached mapping via the GTT. * * Write access through the GTT is not quite fully coherent. On low power * systems especially, like modern Atoms, we can observe reads from RAM before * the write via GTT has landed. A write memory barrier that flushes the Write * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later * read after the write as the GTT write suffers a small delay through the GTT * indirection. The kernel uses an uncached mmio read to ensure the GTT write * is ordered with reads (either by the GPU, WB or WC) and unconditionally * flushes prior to execbuf submission. However, if we are not informing the * kernel about our GTT writes, it will not flush before earlier access, such * as when using the cmdparser. Similarly, we need to be careful if we should * ever issue a CPU read immediately following a GTT write. * * Telling the kernel about write access also has one more important * side-effect. Upon receiving notification about the write, it cancels any * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by * either SW_FINISH or DIRTYFB. The presumption is that we never write to the * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR * tracking is handled on the buffer exchange instead. */ static void * iris_bo_map_gtt(struct pipe_debug_callback *dbg, struct iris_bo *bo, unsigned flags) { struct iris_bufmgr *bufmgr = bo->bufmgr; /* Get a mapping of the buffer if we haven't before. */ if (bo->map_gtt == NULL) { DBG("bo_map_gtt: mmap %d (%s)\n", bo->gem_handle, bo->name); struct drm_i915_gem_mmap_gtt mmap_arg = { .handle = bo->gem_handle }; /* Get the fake offset back... */ int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg); if (ret != 0) { DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n", __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno)); return NULL; } /* and mmap it. */ void *map = mmap(0, bo->size, PROT_READ | PROT_WRITE, MAP_SHARED, bufmgr->fd, mmap_arg.offset); if (map == MAP_FAILED) { DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno)); return NULL; } /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will * already intercept this mmap call. However, for consistency between * all the mmap paths, we mark the pointer as defined now and mark it * as inaccessible afterwards. */ VG_DEFINED(map, bo->size); if (p_atomic_cmpxchg(&bo->map_gtt, NULL, map)) { VG_NOACCESS(map, bo->size); munmap(map, bo->size); } } assert(bo->map_gtt); DBG("bo_map_gtt: %d (%s) -> %p, ", bo->gem_handle, bo->name, bo->map_gtt); print_flags(flags); if (!(flags & MAP_ASYNC)) { bo_wait_with_stall_warning(dbg, bo, "GTT mapping"); } return bo->map_gtt; } static bool can_map_cpu(struct iris_bo *bo, unsigned flags) { if (bo->cache_coherent) return true; /* Even if the buffer itself is not cache-coherent (such as a scanout), on * an LLC platform reads always are coherent (as they are performed via the * central system agent). It is just the writes that we need to take special * care to ensure that land in main memory and not stick in the CPU cache. */ if (!(flags & MAP_WRITE) && bo->bufmgr->has_llc) return true; /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid * across batch flushes where the kernel will change cache domains of the * bo, invalidating continued access to the CPU mmap on non-LLC device. * * Similarly, ASYNC typically means that the buffer will be accessed via * both the CPU and the GPU simultaneously. Batches may be executed that * use the BO even while it is mapped. While OpenGL technically disallows * most drawing while non-persistent mappings are active, we may still use * the GPU for blits or other operations, causing batches to happen at * inconvenient times. * * If RAW is set, we expect the caller to be able to handle a WC buffer * more efficiently than the involuntary clflushes. */ if (flags & (MAP_PERSISTENT | MAP_COHERENT | MAP_ASYNC | MAP_RAW)) return false; return !(flags & MAP_WRITE); } void * iris_bo_map(struct pipe_debug_callback *dbg, struct iris_bo *bo, unsigned flags) { if (bo->tiling_mode != I915_TILING_NONE && !(flags & MAP_RAW)) return iris_bo_map_gtt(dbg, bo, flags); void *map; if (can_map_cpu(bo, flags)) map = iris_bo_map_cpu(dbg, bo, flags); else map = iris_bo_map_wc(dbg, bo, flags); /* Allow the attempt to fail by falling back to the GTT where necessary. * * Not every buffer can be mmaped directly using the CPU (or WC), for * example buffers that wrap stolen memory or are imported from other * devices. For those, we have little choice but to use a GTT mmapping. * However, if we use a slow GTT mmapping for reads where we expected fast * access, that order of magnitude difference in throughput will be clearly * expressed by angry users. * * We skip MAP_RAW because we want to avoid map_gtt's fence detiling. */ if (!map && !(flags & MAP_RAW)) { perf_debug(dbg, "Fallback GTT mapping for %s with access flags %x\n", bo->name, flags); map = iris_bo_map_gtt(dbg, bo, flags); } return map; } /** Waits for all GPU rendering with the object to have completed. */ void iris_bo_wait_rendering(struct iris_bo *bo) { /* We require a kernel recent enough for WAIT_IOCTL support. * See intel_init_bufmgr() */ iris_bo_wait(bo, -1); } /** * Waits on a BO for the given amount of time. * * @bo: buffer object to wait for * @timeout_ns: amount of time to wait in nanoseconds. * If value is less than 0, an infinite wait will occur. * * Returns 0 if the wait was successful ie. the last batch referencing the * object has completed within the allotted time. Otherwise some negative return * value describes the error. Of particular interest is -ETIME when the wait has * failed to yield the desired result. * * Similar to iris_bo_wait_rendering except a timeout parameter allows * the operation to give up after a certain amount of time. Another subtle * difference is the internal locking semantics are different (this variant does * not hold the lock for the duration of the wait). This makes the wait subject * to a larger userspace race window. * * The implementation shall wait until the object is no longer actively * referenced within a batch buffer at the time of the call. The wait will * not guarantee that the buffer is re-issued via another thread, or an flinked * handle. Userspace must make sure this race does not occur if such precision * is important. * * Note that some kernels have broken the inifite wait for negative values * promise, upgrade to latest stable kernels if this is the case. */ int iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns) { struct iris_bufmgr *bufmgr = bo->bufmgr; /* If we know it's idle, don't bother with the kernel round trip */ if (bo->idle && !bo->external) return 0; struct drm_i915_gem_wait wait = { .bo_handle = bo->gem_handle, .timeout_ns = timeout_ns, }; int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_WAIT, &wait); if (ret != 0) return -errno; bo->idle = true; return ret; } void iris_bufmgr_destroy(struct iris_bufmgr *bufmgr) { mtx_destroy(&bufmgr->lock); /* Free any cached buffer objects we were going to reuse */ for (int i = 0; i < bufmgr->num_buckets; i++) { struct bo_cache_bucket *bucket = &bufmgr->cache_bucket[i]; list_for_each_entry_safe(struct iris_bo, bo, &bucket->head, head) { list_del(&bo->head); bo_free(bo); } } _mesa_hash_table_destroy(bufmgr->name_table, NULL); _mesa_hash_table_destroy(bufmgr->handle_table, NULL); for (int z = 0; z < IRIS_MEMZONE_COUNT; z++) { if (z != IRIS_MEMZONE_BINDER) util_vma_heap_finish(&bufmgr->vma_allocator[z]); } free(bufmgr); } static int bo_set_tiling_internal(struct iris_bo *bo, uint32_t tiling_mode, uint32_t stride) { struct iris_bufmgr *bufmgr = bo->bufmgr; struct drm_i915_gem_set_tiling set_tiling; int ret; if (bo->global_name == 0 && tiling_mode == bo->tiling_mode && stride == bo->stride) return 0; memset(&set_tiling, 0, sizeof(set_tiling)); do { /* set_tiling is slightly broken and overwrites the * input on the error path, so we have to open code * drm_ioctl. */ set_tiling.handle = bo->gem_handle; set_tiling.tiling_mode = tiling_mode; set_tiling.stride = stride; ret = ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling); } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); if (ret == -1) return -errno; bo->tiling_mode = set_tiling.tiling_mode; bo->swizzle_mode = set_tiling.swizzle_mode; bo->stride = set_tiling.stride; return 0; } int iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode, uint32_t *swizzle_mode) { *tiling_mode = bo->tiling_mode; *swizzle_mode = bo->swizzle_mode; return 0; } struct iris_bo * iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd) { uint32_t handle; struct iris_bo *bo; mtx_lock(&bufmgr->lock); int ret = drmPrimeFDToHandle(bufmgr->fd, prime_fd, &handle); if (ret) { DBG("import_dmabuf: failed to obtain handle from fd: %s\n", strerror(errno)); mtx_unlock(&bufmgr->lock); return NULL; } /* * See if the kernel has already returned this buffer to us. Just as * for named buffers, we must not create two bo's pointing at the same * kernel object */ bo = hash_find_bo(bufmgr->handle_table, handle); if (bo) { iris_bo_reference(bo); goto out; } bo = bo_calloc(); if (!bo) goto out; p_atomic_set(&bo->refcount, 1); /* Determine size of bo. The fd-to-handle ioctl really should * return the size, but it doesn't. If we have kernel 3.12 or * later, we can lseek on the prime fd to get the size. Older * kernels will just fail, in which case we fall back to the * provided (estimated or guess size). */ ret = lseek(prime_fd, 0, SEEK_END); if (ret != -1) bo->size = ret; bo->bufmgr = bufmgr; bo->gem_handle = handle; _mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo); bo->name = "prime"; bo->reusable = false; bo->external = true; bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED; bo->gtt_offset = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 1); struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle }; if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling)) goto err; bo->tiling_mode = get_tiling.tiling_mode; bo->swizzle_mode = get_tiling.swizzle_mode; /* XXX stride is unknown */ out: mtx_unlock(&bufmgr->lock); return bo; err: bo_free(bo); mtx_unlock(&bufmgr->lock); return NULL; } static void iris_bo_make_external_locked(struct iris_bo *bo) { if (!bo->external) { _mesa_hash_table_insert(bo->bufmgr->handle_table, &bo->gem_handle, bo); bo->external = true; } } static void iris_bo_make_external(struct iris_bo *bo) { struct iris_bufmgr *bufmgr = bo->bufmgr; if (bo->external) return; mtx_lock(&bufmgr->lock); iris_bo_make_external_locked(bo); mtx_unlock(&bufmgr->lock); } int iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd) { struct iris_bufmgr *bufmgr = bo->bufmgr; iris_bo_make_external(bo); if (drmPrimeHandleToFD(bufmgr->fd, bo->gem_handle, DRM_CLOEXEC, prime_fd) != 0) return -errno; bo->reusable = false; return 0; } uint32_t iris_bo_export_gem_handle(struct iris_bo *bo) { iris_bo_make_external(bo); return bo->gem_handle; } int iris_bo_flink(struct iris_bo *bo, uint32_t *name) { struct iris_bufmgr *bufmgr = bo->bufmgr; if (!bo->global_name) { struct drm_gem_flink flink = { .handle = bo->gem_handle }; if (drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_FLINK, &flink)) return -errno; mtx_lock(&bufmgr->lock); if (!bo->global_name) { iris_bo_make_external_locked(bo); bo->global_name = flink.name; _mesa_hash_table_insert(bufmgr->name_table, &bo->global_name, bo); } mtx_unlock(&bufmgr->lock); bo->reusable = false; } *name = bo->global_name; return 0; } static void add_bucket(struct iris_bufmgr *bufmgr, int size) { unsigned int i = bufmgr->num_buckets; assert(i < ARRAY_SIZE(bufmgr->cache_bucket)); list_inithead(&bufmgr->cache_bucket[i].head); bufmgr->cache_bucket[i].size = size; bufmgr->num_buckets++; assert(bucket_for_size(bufmgr, size) == &bufmgr->cache_bucket[i]); assert(bucket_for_size(bufmgr, size - 2048) == &bufmgr->cache_bucket[i]); assert(bucket_for_size(bufmgr, size + 1) != &bufmgr->cache_bucket[i]); } static void init_cache_buckets(struct iris_bufmgr *bufmgr) { uint64_t size, cache_max_size = 64 * 1024 * 1024; /* OK, so power of two buckets was too wasteful of memory. * Give 3 other sizes between each power of two, to hopefully * cover things accurately enough. (The alternative is * probably to just go for exact matching of sizes, and assume * that for things like composited window resize the tiled * width/height alignment and rounding of sizes to pages will * get us useful cache hit rates anyway) */ add_bucket(bufmgr, PAGE_SIZE); add_bucket(bufmgr, PAGE_SIZE * 2); add_bucket(bufmgr, PAGE_SIZE * 3); /* Initialize the linked lists for BO reuse cache. */ for (size = 4 * PAGE_SIZE; size <= cache_max_size; size *= 2) { add_bucket(bufmgr, size); add_bucket(bufmgr, size + size * 1 / 4); add_bucket(bufmgr, size + size * 2 / 4); add_bucket(bufmgr, size + size * 3 / 4); } }
/* * Copies in the user's binning command list and generates the validated bin * CL, along with associated data (shader records, uniforms). */ static int vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) { struct drm_vc4_submit_cl *args = exec->args; void *temp = NULL; void *bin; int ret = 0; uint32_t bin_offset = 0; uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size, 16); uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size; uint32_t exec_size = uniforms_offset + args->uniforms_size; uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) * args->shader_rec_count); if (uniforms_offset < shader_rec_offset || exec_size < uniforms_offset || args->shader_rec_count >= (UINT_MAX / sizeof(struct vc4_shader_state)) || temp_size < exec_size) { DRM_ERROR("overflow in exec arguments\n"); goto fail; } /* Allocate space where we'll store the copied in user command lists * and shader records. * * We don't just copy directly into the BOs because we need to * read the contents back for validation, and I think the * bo->vaddr is uncached access. */ temp = kmalloc(temp_size, GFP_KERNEL); if (!temp) { DRM_ERROR("Failed to allocate storage for copying " "in bin/render CLs.\n"); ret = -ENOMEM; goto fail; } bin = temp + bin_offset; exec->shader_rec_u = temp + shader_rec_offset; exec->uniforms_u = temp + uniforms_offset; exec->shader_state = temp + exec_size; exec->shader_state_size = args->shader_rec_count; ret = copy_from_user(bin, (void __user *)(uintptr_t)args->bin_cl, args->bin_cl_size); if (ret) { DRM_ERROR("Failed to copy in bin cl\n"); goto fail; } ret = copy_from_user(exec->shader_rec_u, (void __user *)(uintptr_t)args->shader_rec, args->shader_rec_size); if (ret) { DRM_ERROR("Failed to copy in shader recs\n"); goto fail; } ret = copy_from_user(exec->uniforms_u, (void __user *)(uintptr_t)args->uniforms, args->uniforms_size); if (ret) { DRM_ERROR("Failed to copy in uniforms cl\n"); goto fail; } exec->exec_bo = drm_gem_cma_create(dev, exec_size); #if 0 if (IS_ERR(exec->exec_bo)) { DRM_ERROR("Couldn't allocate BO for exec\n"); ret = PTR_ERR(exec->exec_bo); exec->exec_bo = NULL; goto fail; } #endif list_addtail(&to_vc4_bo(&exec->exec_bo->base)->unref_head, &exec->unref_list); exec->ct0ca = exec->exec_bo->paddr + bin_offset; exec->bin_u = bin; exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset; exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset; exec->shader_rec_size = args->shader_rec_size; exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset; exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset; exec->uniforms_size = args->uniforms_size; ret = vc4_validate_bin_cl(dev, exec->exec_bo->vaddr + bin_offset, bin, exec); if (ret) goto fail; ret = vc4_validate_shader_recs(dev, exec); fail: kfree(temp); return ret; }
void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred) { list_del(&dep->succ_link); dep->pred = new_pred; list_addtail(&dep->succ_link, &new_pred->succ_list); }