static void txp_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
const struct tgsi_full_instruction * inst = emit_data->inst;
LLVMValueRef src_w;
unsigned chan;
LLVMValueRef coords[5];
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
for (chan = 0; chan < 3; chan++ ) {
LLVMValueRef arg = lp_build_emit_fetch(bld_base,
emit_data->inst, 0, chan);
coords[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_DIV, arg, src_w);
}
coords[3] = bld_base->base.one;
if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, NULL);
}
emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
coords, 4);
emit_data->arg_count = 1;
}
static void emit_iabs(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
emit_data->output[emit_data->chan] =
lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_IMAX,
emit_data->args[0],
LLVMBuildNeg(builder,
emit_data->args[0], ""));
}
/* 1/sqrt is translated to rsq for f32 if fp32 denormals are not enabled in
* the target machine. f64 needs global unsafe math flags to get rsq. */
static void emit_rsq(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
LLVMValueRef sqrt =
lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_SQRT,
emit_data->args[0]);
emit_data->output[emit_data->chan] =
lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_DIV,
bld_base->base.one, sqrt);
}
static void txp_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMValueRef src_w;
unsigned chan;
LLVMValueRef coords[4];
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
for (chan = 0; chan < 3; chan++ ) {
LLVMValueRef arg = lp_build_emit_fetch(bld_base,
emit_data->inst, 0, chan);
coords[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_DIV, arg, src_w);
}
coords[3] = bld_base->base.one;
emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
coords, 4);
emit_data->arg_count = 1;
}
static void llvm_emit_tex(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
struct gallivm_state * gallivm = bld_base->base.gallivm;
LLVMValueRef args[7];
unsigned c, sampler_src;
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
switch (emit_data->inst->Instruction.Opcode) {
case TGSI_OPCODE_TXQ: {
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
ctx->uses_tex_buffers = true;
bool isEgPlus = (ctx->chip_class >= EVERGREEN);
LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm,
isEgPlus ? 0 : 1);
LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, offset,
LLVM_R600_BUFFER_INFO_CONST_BUFFER);
if (!isEgPlus) {
LLVMValueRef maskval[4] = {
lp_build_const_int32(gallivm, 1),
lp_build_const_int32(gallivm, 2),
lp_build_const_int32(gallivm, 3),
lp_build_const_int32(gallivm, 0),
};
LLVMValueRef mask = LLVMConstVector(maskval, 4);
cvecval = LLVMBuildShuffleVector(gallivm->builder, cvecval, cvecval,
mask, "");
}
emit_data->output[0] = cvecval;
return;
}
case TGSI_OPCODE_TXF: {
args[0] = LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], lp_build_const_int32(gallivm, 0), "");
args[1] = lp_build_const_int32(gallivm, R600_MAX_CONST_BUFFERS);
emit_data->output[0] = build_intrinsic(gallivm->builder,
"llvm.R600.load.texbuf",
emit_data->dst_type, args, 2, LLVMReadNoneAttribute);
if (ctx->chip_class >= EVERGREEN)
return;
ctx->uses_tex_buffers = true;
LLVMDumpValue(emit_data->output[0]);
emit_data->output[0] = LLVMBuildBitCast(gallivm->builder,
emit_data->output[0], LLVMVectorType(bld_base->base.int_elem_type, 4),
"");
LLVMValueRef Mask = llvm_load_const_buffer(bld_base,
lp_build_const_int32(gallivm, 0),
LLVM_R600_BUFFER_INFO_CONST_BUFFER);
Mask = LLVMBuildBitCast(gallivm->builder, Mask,
LLVMVectorType(bld_base->base.int_elem_type, 4), "");
emit_data->output[0] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_AND,
emit_data->output[0],
Mask);
LLVMValueRef WComponent = LLVMBuildExtractElement(gallivm->builder,
emit_data->output[0], lp_build_const_int32(gallivm, 3), "");
Mask = llvm_load_const_buffer(bld_base, lp_build_const_int32(gallivm, 1),
LLVM_R600_BUFFER_INFO_CONST_BUFFER);
Mask = LLVMBuildExtractElement(gallivm->builder, Mask,
lp_build_const_int32(gallivm, 0), "");
Mask = LLVMBuildBitCast(gallivm->builder, Mask,
bld_base->base.int_elem_type, "");
WComponent = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_OR,
WComponent, Mask);
emit_data->output[0] = LLVMBuildInsertElement(gallivm->builder,
emit_data->output[0], WComponent, lp_build_const_int32(gallivm, 3), "");
emit_data->output[0] = LLVMBuildBitCast(gallivm->builder,
emit_data->output[0], LLVMVectorType(bld_base->base.elem_type, 4), "");
}
return;
default:
break;
}
}
if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TEX ||
emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
LLVMValueRef Vector[4] = {
LLVMBuildExtractElement(gallivm->builder, emit_data->args[0],
lp_build_const_int32(gallivm, 0), ""),
LLVMBuildExtractElement(gallivm->builder, emit_data->args[0],
lp_build_const_int32(gallivm, 1), ""),
LLVMBuildExtractElement(gallivm->builder, emit_data->args[0],
lp_build_const_int32(gallivm, 2), ""),
LLVMBuildExtractElement(gallivm->builder, emit_data->args[0],
lp_build_const_int32(gallivm, 3), ""),
};
switch (emit_data->inst->Texture.Texture) {
case TGSI_TEXTURE_2D:
case TGSI_TEXTURE_RECT:
Vector[2] = Vector[3] = LLVMGetUndef(bld_base->base.elem_type);
break;
case TGSI_TEXTURE_1D:
Vector[1] = Vector[2] = Vector[3] = LLVMGetUndef(bld_base->base.elem_type);
break;
default:
break;
}
args[0] = lp_build_gather_values(gallivm, Vector, 4);
} else {
args[0] = emit_data->args[0];
}
assert(emit_data->arg_count + 2 <= Elements(args));
for (c = 1; c < emit_data->arg_count; ++c)
args[c] = emit_data->args[c];
if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
args[1] = LLVMBuildShl(gallivm->builder, args[1], lp_build_const_int32(gallivm, 1), "");
args[2] = LLVMBuildShl(gallivm->builder, args[2], lp_build_const_int32(gallivm, 1), "");
args[3] = LLVMBuildShl(gallivm->builder, args[3], lp_build_const_int32(gallivm, 1), "");
}
sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Src[sampler_src].Register.Index + R600_MAX_CONST_BUFFERS);
args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Src[sampler_src].Register.Index);
args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Texture.Texture);
if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
(emit_data->inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
emit_data->inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
switch (emit_data->inst->Texture.Texture) {
case TGSI_TEXTURE_2D_MSAA:
args[6] = lp_build_const_int32(gallivm, TGSI_TEXTURE_2D);
break;
case TGSI_TEXTURE_2D_ARRAY_MSAA:
args[6] = lp_build_const_int32(gallivm, TGSI_TEXTURE_2D_ARRAY);
break;
default:
break;
}
if (ctx->has_compressed_msaa_texturing) {
LLVMValueRef ldptr_args[10] = {
args[0], // Coord
args[1], // Offset X
args[2], // Offset Y
args[3], // Offset Z
args[4],
args[5],
lp_build_const_int32(gallivm, 1),
lp_build_const_int32(gallivm, 1),
lp_build_const_int32(gallivm, 1),
lp_build_const_int32(gallivm, 1)
};
LLVMValueRef ptr = build_intrinsic(gallivm->builder,
"llvm.R600.ldptr",
emit_data->dst_type, ldptr_args, 10, LLVMReadNoneAttribute);
LLVMValueRef Tmp = LLVMBuildExtractElement(gallivm->builder, args[0],
lp_build_const_int32(gallivm, 3), "");
Tmp = LLVMBuildMul(gallivm->builder, Tmp,
lp_build_const_int32(gallivm, 4), "");
LLVMValueRef ResX = LLVMBuildExtractElement(gallivm->builder, ptr,
lp_build_const_int32(gallivm, 0), "");
ResX = LLVMBuildBitCast(gallivm->builder, ResX,
bld_base->base.int_elem_type, "");
Tmp = LLVMBuildLShr(gallivm->builder, ResX, Tmp, "");
Tmp = LLVMBuildAnd(gallivm->builder, Tmp,
lp_build_const_int32(gallivm, 0xF), "");
args[0] = LLVMBuildInsertElement(gallivm->builder, args[0], Tmp,
lp_build_const_int32(gallivm, 3), "");
args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Texture.Texture);
}
}
emit_data->output[0] = build_intrinsic(gallivm->builder,
action->intr_name,
emit_data->dst_type, args, c, LLVMReadNoneAttribute);
if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
((emit_data->inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
if (emit_data->inst->Dst[0].Register.WriteMask & 4) {
LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, 0);
LLVMValueRef ZLayer = LLVMBuildExtractElement(gallivm->builder,
llvm_load_const_buffer(bld_base, offset, CONSTANT_TXQ_BUFFER),
lp_build_const_int32(gallivm, 0), "");
emit_data->output[0] = LLVMBuildInsertElement(gallivm->builder, emit_data->output[0], ZLayer, lp_build_const_int32(gallivm, 2), "");
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
ctx->has_txq_cube_array_z_comp = true;
}
}
