void up_irqinitialize(void) { uintptr_t regaddr; int nintlines; int i; /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt * lines that the NVIC supports, defined in groups of 32. That is, * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). * * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers * 1 -> 64 " " " ", 2 enable registers, 16 priority registers * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers * ... */ nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; /* Disable all interrupts. There are nintlines interrupt enable * registers. */ for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; i > 0; i--, regaddr += 4) { putreg32(0, regaddr); } /* Make sure that we are using the correct vector table. The default * vector address is 0x0000:0000 but if we are executing code that is * positioned in SRAM or in external FLASH, then we may need to reset * the interrupt vector so that it refers to the table in SRAM or in * external FLASH. */ putreg32((uint32_t)_vectors, NVIC_VECTAB); /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. * * But even in this case NVIC_VECTAB has to point to the initial table * because up_ramvec_initialize() initializes RAM table from table * pointed by NVIC_VECTAB register. */ #ifdef CONFIG_ARCH_RAMVECTORS up_ramvec_initialize(); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); /* Now set all of the interrupt lines to the default priority. There are * nintlines * 8 priority registers. */ for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; i > 0; i--, regaddr += 4) { putreg32(DEFPRIORITY32, regaddr); } /* currents_regs is non-NULL only while processing an interrupt */ CURRENT_REGS = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(LPC17_IRQ_SVCALL, up_svcall); irq_attach(LPC17_IRQ_HARDFAULT, up_hardfault); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI lpc17_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); up_enable_irq(LPC17_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES irq_attach(LPC17_IRQ_NMI, lpc17_nmi); #ifndef CONFIG_ARM_MPU irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); #endif irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault); irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault); irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv); irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor); irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved); #endif lpc17_dumpnvic("initial", LPC17_IRQ_NIRQS); /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ #ifdef CONFIG_GPIO_IRQ lpc17_gpioirqinitialize(); #endif /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS up_irq_enable(); #endif }
void up_irqinitialize(void) { /* Disable all interrupts */ putreg32(0, NVIC_IRQ0_31_ENABLE); /* Set all interrrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); /* currents_regs is non-NULL only while processing an interrupt */ current_regs = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(LPC17_IRQ_SVCALL, up_svcall); irq_attach(LPC17_IRQ_HARDFAULT, up_hardfault); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARMV7M_MPU irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); up_enable_irq(LPC17_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG irq_attach(LPC17_IRQ_NMI, lpc17_nmi); #ifndef CONFIG_ARMV7M_MPU irq_attach(LPC17_IRQ_MEMFAULT, up_memfault); #endif irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault); irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault); irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv); irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor); irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved); #endif lpc17_dumpnvic("initial", LPC17_IRQ_NIRQS); /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ #ifdef CONFIG_GPIO_IRQ lpc17_gpioirqinitialize(); #endif /* And finally, enable interrupts */ #ifndef CONFIG_SUPPRESS_INTERRUPTS setbasepri(NVIC_SYSH_PRIORITY_MAX); irqrestore(0); #endif }