void arm_boot(void)
{
/* __start provided the basic MMU mappings for SRAM. Now provide mappings for all
* IO regions (Including the vector region).
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
up_setupmappings();
/* Provide a special mapping for the IRAM interrupt vector positioned in high
* memory.
*/
#ifndef CONFIG_ARCH_LOWVECTORS
up_vectormapping();
#endif
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* Setup up vector block. _vector_start and _vector_end are exported from
* up_vector.S
*/
up_copyvectorblock();
/* Reset all clocks */
lpc31_resetclks();
/* Initialize the PLLs */
lpc31_hp1pllconfig();
lpc31_hp0pllconfig();
/* Initialize clocking to settings provided by board-specific logic */
lpc31_clkinit(&g_boardclks);
/* Map first 4KB of ARM space to ISRAM area */
putreg32(LPC31_INTSRAM0_PADDR, LPC31_SYSCREG_ARM926SHADOWPTR);
/* Perform common, low-level chip initialization (might do nothing) */
lpc31_lowsetup();
/* Perform early serial initialization if we are going to use the serial driver */
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
#endif
/* Perform board-specific initialization */
lpc31_boardinitialize();
}
void lpc31_clkinit(const struct lpc31_clkinit_s* cfg)
{
struct lpc31_domainconfig_s domain;
/* Reset all clocks and connect them to FFAST */
lpc31_resetclks();
/* Initialize Domain0 = SYS_BASE clocks */
domain.dmnid = DOMAINID_SYS;
domain.finsel = cfg->domain0.finsel;
domain.clk1 = CLKID_SYSBASE_FIRST;
domain.nclks = (CLKID_SYSBASE_LAST - CLKID_SYSBASE_FIRST) + 1;
domain.fdiv1 = FRACDIV_BASE0_LOW;
domain.nfdiv = FRACDIV_BASE0_CNT;
domain.sub = cfg->domain0.sub;
lpc31_domaininit(&domain);
/* Initialize Domain1 = AHB0APB0_BASE clocks */
domain.dmnid = DOMAINID_AHB0APB0;
domain.finsel = cfg->domain1.finsel;
domain.clk1 = CLKID_AHB0APB0_FIRST;
domain.nclks = (CLKID_AHB0APB0_LAST - CLKID_AHB0APB0_FIRST) + 1;
domain.fdiv1 = FRACDIV_BASE1_LOW;
domain.nfdiv = FRACDIV_BASE1_CNT;
domain.sub = cfg->domain1.sub;
lpc31_domaininit(&domain);
/* Initialize Domain2 = AHB0APB1_BASE clocks */
domain.dmnid = DOMAINID_AHB0APB1;
domain.finsel = cfg->domain2.finsel;
domain.clk1 = CLKID_AHB0APB1_FIRST;
domain.nclks = (CLKID_AHB0APB1_LAST - CLKID_AHB0APB1_FIRST) + 1;
domain.fdiv1 = FRACDIV_BASE2_LOW;
domain.nfdiv = FRACDIV_BASE2_CNT;
domain.sub = cfg->domain2.sub;
lpc31_domaininit(&domain);
/* Initialize Domain3 = AHB0APB2_BASE clocks */
domain.dmnid = DOMAINID_AHB0APB2;
domain.finsel = cfg->domain3.finsel;
domain.clk1 = CLKID_AHB0APB2_FIRST;
domain.nclks = (CLKID_AHB0APB2_LAST - CLKID_AHB0APB2_FIRST) + 1;
domain.fdiv1 = FRACDIV_BASE3_LOW;
domain.nfdiv = FRACDIV_BASE3_CNT;
domain.sub = cfg->domain3.sub;
lpc31_domaininit(&domain);
/* Initialize Domain4 = AHB0APB3_BASE clocks */
domain.dmnid = DOMAINID_AHB0APB3;
domain.finsel = cfg->domain4.finsel;
domain.clk1 = CLKID_AHB0APB3_FIRST;
domain.nclks = (CLKID_AHB0APB3_LAST - CLKID_AHB0APB3_FIRST) + 1;
domain.fdiv1 = FRACDIV_BASE4_LOW;
domain.nfdiv = FRACDIV_BASE4_CNT;
domain.sub = cfg->domain4.sub;
lpc31_domaininit(&domain);
/* Initialize Domain5 = PCM_BASE clocks */
domain.dmnid = DOMAINID_PCM;
domain.finsel = cfg->domain5.finsel;
domain.clk1 = CLKID_PCM_FIRST;
domain.nclks = 1;
domain.fdiv1 = FRACDIV_BASE5_LOW;
domain.nfdiv = FRACDIV_BASE5_CNT;
domain.sub = cfg->domain5.sub;
lpc31_domaininit(&domain);
/* Initialize Domain6 = UART_BASE clocks */
domain.dmnid = DOMAINID_UART;
domain.finsel = cfg->domain6.finsel;
domain.clk1 = CLKID_UART_FIRST;
domain.nclks = 1;
domain.fdiv1 = FRACDIV_BASE6_LOW;
domain.nfdiv = FRACDIV_BASE6_CNT;
domain.sub = cfg->domain6.sub;
lpc31_domaininit(&domain);
/* Initialize Domain7 = CLK1024FS_BASE clocks */
domain.dmnid = DOMAINID_CLK1024FS;
domain.finsel = cfg->domain7.finsel;
domain.clk1 = CLKID_CLK1024FS_FIRST;
domain.nclks = (CLKID_CLK1024FS_LAST - CLKID_CLK1024FS_FIRST) + 1;
domain.fdiv1 = FRACDIV_BASE7_LOW;
domain.nfdiv = FRACDIV_BASE7_CNT;
domain.sub = cfg->domain7.sub;
lpc31_domaininit(&domain);
/* Initialize Domain8 = I2SRX_BCK0_BASE clocks */
lpc31_selectfreqin(DOMAINID_BCK0, cfg->domain8.finsel);
/* Initialize Domain9 = I2SRX_BCK1_BASE clocks */
lpc31_selectfreqin(DOMAINID_BCK1, cfg->domain9.finsel);
/* Initialize Domain10 = SPI_BASE clocks */
domain.dmnid = DOMAINID_SPI;
domain.finsel = cfg->domain10.finsel;
domain.clk1 = CLKID_SPI_FIRST;
domain.nclks = (CLKID_SPI_LAST - CLKID_SPI_FIRST) + 1;
domain.fdiv1 = FRACDIV_BASE10_LOW;
domain.nfdiv = FRACDIV_BASE10_CNT;
domain.sub = cfg->domain10.sub;
lpc31_domaininit(&domain);
/* Initialize Domain11 = SYSCLK_O_BASE clocks */
lpc31_selectfreqin(DOMAINID_SYSCLKO, cfg->domain11.finsel);
/* Initialize Dynamic fractional dividers -- to be provided */
}
