void lpcrst_interrupt(enum gpio_signal signal)
{
if (lpc_get_pltrst_asserted())
/* Store port 80 reset event */
port_80_write(PORT_80_EVENT_RESET);
CPRINTS("LPC RESET# %sasserted",
lpc_get_pltrst_asserted() ? "" : "de");
}
/* Initialize host settings by interrupt */
void lpc_lreset_pltrst_handler(void)
{
int pltrst_asserted;
/* Clear pending bit of WUI */
SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7);
/* Ignore PLTRST# from SOC if it is not valid */
if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid())
return;
pltrst_asserted = lpc_get_pltrst_asserted();
ccprintf("LPC RESET# %sasserted",
pltrst_asserted ? "" : "de");
/*
* Once LRESET is de-asserted (low -> high), we need to initialize lpc
* settings once. If RSTCTL_LRESET_PLTRST_MODE is active, LPC registers
* won't be reset by Host domain reset but Core domain does.
*/
if (!pltrst_asserted)
host_register_init();
else {
#ifdef CONFIG_CHIPSET_RESET_HOOK
/* Notify HOOK_CHIPSET_RESET */
hook_call_deferred(&lpc_chipset_reset_data, MSEC);
#endif
}
}
void girq19_interrupt(void)
{
/* Check interrupt result for LRESET# trigger */
if (MEC1322_INT_RESULT(19) & (1 << 1)) {
/* Initialize LPC module when LRESET# is deasserted */
if (!lpc_get_pltrst_asserted()) {
setup_lpc();
} else {
/* Store port 80 reset event */
port_80_write(PORT_80_EVENT_RESET);
}
CPRINTS("LPC RESET# %sasserted",
lpc_get_pltrst_asserted() ? "" : "de");
/* Clear interrupt source */
MEC1322_INT_SOURCE(19) = 1 << 1;
}
}
void girq19_interrupt(void)
{
/* Check interrupt result for LRESET# trigger */
if (MEC1322_INT_RESULT(19) & (1 << 1)) {
/* Initialize LPC module when LRESET# is deasserted */
if (!lpc_get_pltrst_asserted()) {
setup_lpc();
} else {
/* Store port 80 reset event */
port_80_write(PORT_80_EVENT_RESET);
#ifdef CONFIG_CHIPSET_RESET_HOOK
/* Notify HOOK_CHIPSET_RESET */
hook_call_deferred(&lpc_chipset_reset_data, MSEC);
#endif
}
CPRINTS("LPC RESET# %sasserted",
lpc_get_pltrst_asserted() ? "" : "de");
/* Clear interrupt source */
MEC1322_INT_SOURCE(19) = 1 << 1;
}
}
/* Initialize host settings by interrupt */
void lpc_lreset_pltrst_handler(void)
{
/* Clear pending bit of WUI */
SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7);
/*
* Once LRESET is de-asserted (low -> high), we need to intialize lpc
* settings once. If RSTCTL_LRESET_PLTRST_MODE is active, LPC registers
* won't be reset by Host domain reset but Core domain does.
*/
lpc_host_register_init();
#ifdef CONFIG_CHIPSET_RESET_HOOK
if (lpc_get_pltrst_asserted()) {
/* Notify HOOK_CHIPSET_RESET */
hook_call_deferred(lpc_chipset_reset, MSEC);
}
#endif
}
/**
* LPC interrupt handler
*/
void lpc_interrupt(void)
{
uint32_t mis = LM4_LPC_LPCMIS;
uint32_t st;
/* Clear the interrupt bits we're handling */
LM4_LPC_LPCIC = mis;
#ifdef HAS_TASK_HOSTCMD
/* Handle ACPI command and data writes */
st = LM4_LPC_ST(LPC_CH_ACPI);
if (st & LM4_LPC_ST_FRMH)
handle_acpi_write(st & LM4_LPC_ST_CMD);
/* Handle user command writes */
st = LM4_LPC_ST(LPC_CH_CMD);
if (st & LM4_LPC_ST_FRMH)
handle_host_write(st & LM4_LPC_ST_CMD);
#endif
/*
* Handle port 80 writes (CH0MIS1). Due to crosbug.com/p/12349 the
* interrupt status (mis & LM4_LPC_INT_MASK(LPC_CH_PORT80, 2))
* apparently gets lost on back-to-back writes to port 80, so check the
* FRMH bit in the channel status register to see if a write is
* pending. Loop to handle bursts of back-to-back writes.
*/
while (LM4_LPC_ST(LPC_CH_PORT80) & LM4_LPC_ST_FRMH)
port_80_write(LPC_POOL_PORT80[0]);
#ifdef HAS_TASK_KEYPROTO
/* Handle keyboard interface writes */
st = LM4_LPC_ST(LPC_CH_KEYBOARD);
if (st & LM4_LPC_ST_FRMH)
keyboard_host_write(LPC_POOL_KEYBOARD[0], st & LM4_LPC_ST_CMD);
if (mis & LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 1)) {
/* Host read data; wake up task to send remaining bytes */
task_wake(TASK_ID_KEYPROTO);
}
#endif
#ifdef CONFIG_UART_HOST
/* Handle COMx */
if (lpc_comx_has_char()) {
/* Copy a character to the UART if there's space */
if (uart_comx_putc_ok())
uart_comx_putc(lpc_comx_get_char());
}
#endif
/* Debugging: print changes to LPC0RESET */
if (mis & (1 << 31)) {
if (LM4_LPC_LPCSTS & (1 << 10)) {
int i;
/* Store port 80 reset event */
port_80_write(PORT_80_EVENT_RESET);
/*
* Workaround for crosbug.com/p/12349; clear all FRMH
* bits so host writes will trigger interrupts.
*/
for (i = 0; i < 8; i++)
LM4_LPC_ST(i) &= ~LM4_LPC_ST_FRMH;
}
CPRINTS("LPC RESET# %sasserted",
lpc_get_pltrst_asserted() ? "" : "de");
}
}
